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| author | Craig Topper <craig.topper@intel.com> | 2018-07-17 20:16:18 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-07-17 20:16:18 +0000 |
| commit | 9ef92865ecca5bbe3bf9ef10a3bb569c16af8bdd (patch) | |
| tree | 1214882d5c749311a9f13d22498b621e004f6134 /llvm/test | |
| parent | c0f2e306f2388a0ad1f10e4e9cc8157121d4f4e5 (diff) | |
| download | bcm5719-llvm-9ef92865ecca5bbe3bf9ef10a3bb569c16af8bdd.tar.gz bcm5719-llvm-9ef92865ecca5bbe3bf9ef10a3bb569c16af8bdd.zip | |
[X86] Add patterns for folding full vector load into MOVHPS and MOVLPS with SSE1 only.
llvm-svn: 337320
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-sse1.ll | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-sse1.ll b/llvm/test/CodeGen/X86/vector-shuffle-sse1.ll index 5f8c21bd852..dda46e062d5 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-sse1.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-sse1.ll @@ -298,9 +298,7 @@ define <4 x float> @shuffle_mem_v4f32_6723(<4 x float> %a, <4 x float>* %pb) { define <4 x float> @shuffle_mem_v4f32_4523(<4 x float> %a, <4 x float>* %pb) { ; SSE1-LABEL: shuffle_mem_v4f32_4523: ; SSE1: # %bb.0: -; SSE1-NEXT: movaps (%rdi), %xmm1 -; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3] -; SSE1-NEXT: movaps %xmm1, %xmm0 +; SSE1-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3] ; SSE1-NEXT: retq %b = load <4 x float>, <4 x float>* %pb, align 16 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 3> |
