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| author | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-07-28 19:57:25 +0000 |
|---|---|---|
| committer | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-07-28 19:57:25 +0000 |
| commit | 9ec611486099b37f9d29136562a608c84738eeb5 (patch) | |
| tree | 1f152646d5cc07719c67f2439cb6e636649c0ad3 /llvm/test | |
| parent | a43ce0dc98f9e1af6ca7d0019a4b32ce0c7028ab (diff) | |
| download | bcm5719-llvm-9ec611486099b37f9d29136562a608c84738eeb5.tar.gz bcm5719-llvm-9ec611486099b37f9d29136562a608c84738eeb5.zip | |
[mips][FastISel] Fix generated code for IR's select instruction.
Summary:
Generate correct code for the select instruction by zero-extending
it's boolean/condition operand to GPR-width. This is necessary because
the conditional-move instructions operate on the whole register.
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11506
llvm-svn: 243469
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll index 47b6a895cde..48614444a57 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll @@ -8,7 +8,8 @@ entry: ; FIXME: The following instruction is redundant. ; CHECK: xor $[[T0:[0-9]+]], $4, $zero ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: movn $6, $5, $[[T1]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK-NEXT: movn $6, $5, $[[T2]] ; CHECK: move $2, $6 %cond = icmp ne i1 %j, 0 %res = select i1 %cond, i1 %k, i1 %l @@ -24,7 +25,8 @@ entry: ; CHECK-DAG: seb $[[T1:[0-9]+]], $zero ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]] ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]] - ; CHECK-NEXT: movn $6, $5, $[[T3]] + ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1 + ; CHECK-NEXT: movn $6, $5, $[[T4]] ; CHECK: move $2, $6 %cond = icmp ne i8 %j, 0 %res = select i1 %cond, i8 %k, i8 %l @@ -40,7 +42,8 @@ entry: ; CHECK-DAG: seh $[[T1:[0-9]+]], $zero ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]] ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]] - ; CHECK-NEXT: movn $6, $5, $[[T3]] + ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1 + ; CHECK-NEXT: movn $6, $5, $[[T4]] ; CHECK: move $2, $6 %cond = icmp ne i16 %j, 0 %res = select i1 %cond, i16 %k, i16 %l @@ -54,7 +57,8 @@ entry: ; FIXME: The following instruction is redundant. ; CHECK: xor $[[T0:[0-9]+]], $4, $zero ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: movn $6, $5, $[[T1]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK-NEXT: movn $6, $5, $[[T2]] ; CHECK: move $2, $6 %cond = icmp ne i32 %j, 0 %res = select i1 %cond, i32 %k, i32 %l @@ -69,7 +73,8 @@ entry: ; CHECK-DAG: mtc1 $5, $f1 ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK: movn.s $f0, $f1, $[[T1]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK: movn.s $f0, $f1, $[[T2]] %cond = icmp ne i32 %j, 0 %res = select i1 %cond, float %k, float %l ret float %res @@ -84,7 +89,8 @@ entry: ; CHECK-DAG: ldc1 $f0, 16($sp) ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK: movn.d $f0, $f2, $[[T1]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK: movn.d $f0, $f2, $[[T2]] %cond = icmp ne i32 %j, 0 %res = select i1 %cond, double %k, double %l ret double %res |
