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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-24 06:59:24 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-24 06:59:24 +0000 |
| commit | 9acb9781050ed5e9b7f3a0fa87a49e2770c522d9 (patch) | |
| tree | c65d1653bf0e0ffab1aa7bca07cfec8f0aa0f7ba /llvm/test | |
| parent | 0daeb63f036c48b20c7149d877b72381cc08fd4d (diff) | |
| download | bcm5719-llvm-9acb9781050ed5e9b7f3a0fa87a49e2770c522d9.tar.gz bcm5719-llvm-9acb9781050ed5e9b7f3a0fa87a49e2770c522d9.zip | |
R600: Match rcp node on pre-SI
llvm-svn: 213844
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll | 40 |
1 files changed, 11 insertions, 29 deletions
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll index 8d5d66e149b..df6c3bb6a2c 100644 --- a/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll +++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll @@ -1,65 +1,47 @@ ; RUN: llc -march=r600 -mcpu=SI -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s - ; XUN: llc -march=r600 -mcpu=SI -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG-SAFE -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone - declare float @llvm.sqrt.f32(float) nounwind readnone -declare double @llvm.sqrt.f64(double) nounwind readnone ; FUNC-LABEL: @rcp_f32 ; SI: V_RCP_F32_e32 +; EG: RECIP_IEEE define void @rcp_f32(float addrspace(1)* %out, float %src) nounwind { %rcp = call float @llvm.AMDGPU.rcp.f32(float %src) nounwind readnone store float %rcp, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @rcp_f64 -; SI: V_RCP_F64_e32 -define void @rcp_f64(double addrspace(1)* %out, double %src) nounwind { - %rcp = call double @llvm.AMDGPU.rcp.f64(double %src) nounwind readnone - store double %rcp, double addrspace(1)* %out, align 8 - ret void -} - +; FIXME: Evergreen only ever does unsafe fp math. ; FUNC-LABEL: @rcp_pat_f32 + ; SI-SAFE: V_RCP_F32_e32 ; XSI-SAFE-SPDENORM-NOT: V_RCP_F32_e32 + +; EG: RECIP_IEEE + define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind { %rcp = fdiv float 1.0, %src store float %rcp, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @rcp_pat_f64 -; SI: V_RCP_F64_e32 -define void @rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind { - %rcp = fdiv double 1.0, %src - store double %rcp, double addrspace(1)* %out, align 8 - ret void -} - ; FUNC-LABEL: @rsq_rcp_pat_f32 ; SI-UNSAFE: V_RSQ_F32_e32 ; SI-SAFE: V_SQRT_F32_e32 ; SI-SAFE: V_RCP_F32_e32 + +; EG: RECIPSQRT_IEEE define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind { %sqrt = call float @llvm.sqrt.f32(float %src) nounwind readnone %rcp = call float @llvm.AMDGPU.rcp.f32(float %sqrt) nounwind readnone store float %rcp, float addrspace(1)* %out, align 4 ret void } - -; FUNC-LABEL: @rsq_rcp_pat_f64 -; SI-UNSAFE: V_RSQ_F64_e32 -; SI-SAFE-NOT: V_RSQ_F64_e32 -define void @rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind { - %sqrt = call double @llvm.sqrt.f64(double %src) nounwind readnone - %rcp = call double @llvm.AMDGPU.rcp.f64(double %sqrt) nounwind readnone - store double %rcp, double addrspace(1)* %out, align 8 - ret void -} |
