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| author | Joerg Sonnenberger <joerg@bec.de> | 2014-08-02 15:09:41 +0000 |
|---|---|---|
| committer | Joerg Sonnenberger <joerg@bec.de> | 2014-08-02 15:09:41 +0000 |
| commit | 99ab590ac990e41f390e3be2351e2348f8c6b7df (patch) | |
| tree | ea222e4ecb82cf531e6d573d48de3471b50aeed1 /llvm/test | |
| parent | 466a31eb65339bcd4212ec7b31ceebfd8a4a2b4f (diff) | |
| download | bcm5719-llvm-99ab590ac990e41f390e3be2351e2348f8c6b7df.tar.gz bcm5719-llvm-99ab590ac990e41f390e3be2351e2348f8c6b7df.zip | |
Don't use additional arguments for dss and friends to satisfy DSS_Form,
when let can do the same thing. Keep the 64bit variants as codegen-only.
While they have a different register class, the encoding is the same for
32bit and 64bit mode. Having both present would otherwise confuse the
disassembler.
llvm-svn: 214636
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt | 13 | ||||
| -rw-r--r-- | llvm/test/MC/PowerPC/ppc64-encoding-ext.s | 20 |
2 files changed, 33 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt index 2998e8d1ab7..b55ebce81a2 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt @@ -2255,3 +2255,16 @@ 0x4c 0x00 0x00 0x4e # CHECK: rfmci 0x4c 0x00 0x00 0x4c + +# CHECK: dss 3 +0x7c 0x60 0x06 0x6c +# CHECK: dssall +0x7e 0x00 0x06 0x6c +# CHECK: dst 12, 11, 3 +0x7c 0x6c 0x5a 0xac +# CHECK: dstt 12, 11, 3 +0x7e 0x6c 0x5a 0xac +# CHECK: dstst 12, 11, 3 +0x7c 0x6c 0x5a 0xec +# CHECK: dststt 12, 11, 3 +0x7e 0x6c 0x5a 0xec diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s index 258b594698d..2e9316f848f 100644 --- a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s @@ -3593,3 +3593,23 @@ # CHECK-BE: rfmci # encoding: [0x4c,0x00,0x00,0x4c] # CHECK-LE: rfmci # encoding: [0x4c,0x00,0x00,0x4c] rfmci + +# Altivec Data Stream instruction: +# CHECK-BE: dss 3 # encoding: [0x7c,0x60,0x06,0x6c] +# CHECK-LE: dss 3 # encoding: [0x6c,0x06,0x60,0x7c] + dss 3 +# CHECK-BE: dssall # encoding: [0x7e,0x00,0x06,0x6c] +# CHECK-LE: dssall # encoding: [0x6c,0x06,0x00,0x7e] + dssall +# CHECK-BE: dst 12, 11, 3 # encoding: [0x7c,0x6c,0x5a,0xac] +# CHECK-LE: dst 12, 11, 3 # encoding: [0xac,0x5a,0x6c,0x7c] + dst %r12, %r11, 3 +# CHECK-BE: dstt 12, 11, 3 # encoding: [0x7e,0x6c,0x5a,0xac] +# CHECK-LE: dstt 12, 11, 3 # encoding: [0xac,0x5a,0x6c,0x7e] + dstt %r12, %r11, 3 +# CHECK-BE: dstst 12, 11, 3 # encoding: [0x7c,0x6c,0x5a,0xec] +# CHECK-LE: dstst 12, 11, 3 # encoding: [0xec,0x5a,0x6c,0x7c] + dstst %r12, %r11, 3 +# CHECK-BE: dststt 12, 11, 3 # encoding: [0x7e,0x6c,0x5a,0xec] +# CHECK-LE: dststt 12, 11, 3 # encoding: [0xec,0x5a,0x6c,0x7e] + dststt %r12, %r11, 3 |
