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| author | Derek Schuff <dschuff@google.com> | 2015-12-11 23:49:46 +0000 | 
|---|---|---|
| committer | Derek Schuff <dschuff@google.com> | 2015-12-11 23:49:46 +0000 | 
| commit | 9769debf88170904006b4b16538085e5dbd2ed44 (patch) | |
| tree | b316f68ef161411bf790cf6c5ba27b717873bae5 /llvm/test | |
| parent | e8f9387e0cae74b54a8e77310477626a59a91aed (diff) | |
| download | bcm5719-llvm-9769debf88170904006b4b16538085e5dbd2ed44.tar.gz bcm5719-llvm-9769debf88170904006b4b16538085e5dbd2ed44.zip  | |
[WebAssembly]  Implement prolog/epilog insertion and FrameIndex elimination
Summary:
Use the SP32 physical register as the base for FrameIndex
lowering. Update it and the __stack_pointer global var in the prolog and
epilog. Extend the mapping of virtual registers to wasm locals to
include the physical registers.
Rather than modify the target-independent PrologEpilogInserter (which
asserts that there are no virtual registers left) include a
slightly-modified copy for Wasm that does not have this assertion and
only clears the virtual registers if scavenging was needed (which of
course it isn't for wasm).
Differential Revision: http://reviews.llvm.org/D15344
llvm-svn: 255392
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/userstack.ll | 70 | 
1 files changed, 70 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/WebAssembly/userstack.ll b/llvm/test/CodeGen/WebAssembly/userstack.ll new file mode 100644 index 00000000000..27ff1e192e6 --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/userstack.ll @@ -0,0 +1,70 @@ +; RUN: llc < %s -asm-verbose=false | FileCheck %s +; RUN: llc < %s -asm-verbose=false -fast-isel | FileCheck %s + + +target datalayout = "e-p:32:32-i64:64-n32:64-S128" +target triple = "wasm32-unknown-unknown" + +; CHECK-LABEL: alloca32: +define void @alloca32() { + ; CHECK: i32.const [[L1:.+]]=, __stack_pointer + ; CHECK-NEXT: i32.load [[L1]]=, 0([[L1]]) + ; CHECK-NEXT: i32.const [[L2:.+]]=, 16 + ; CHECK-NEXT: i32.sub [[SP:.+]]=, [[L1]], [[L2]] + %retval = alloca i32 + ; CHECK: i32.const $push[[L3:.+]]=, 0 + ; CHECK: i32.store {{.*}}=, 12([[SP]]), $pop[[L3]] + store i32 0, i32* %retval + ; CHECK: i32.const [[L4:.+]]=, 16 + ; CHECK-NEXT: i32.add [[SP]]=, [[SP]], [[L4]] + ; CHECK-NEXT: i32.const [[L5:.+]]=, __stack_pointer + ; CHECK-NEXT: i32.store [[SP]]=, 0([[L5]]), [[SP]] + ret void +} + +; CHECK-LABEL: alloca3264: +define void @alloca3264() { + ; CHECK: i32.const [[L1:.+]]=, __stack_pointer + ; CHECK-NEXT: i32.load [[L1]]=, 0([[L1]]) + ; CHECK-NEXT: i32.const [[L2:.+]]=, 16 + ; CHECK-NEXT: i32.sub [[SP:.+]]=, [[L1]], [[L2]] + %r1 = alloca i32 + %r2 = alloca double + ; CHECK: i32.const $push[[L3:.+]]=, 0 + ; CHECK: i32.store {{.*}}=, 12([[SP]]), $pop[[L3]] + store i32 0, i32* %r1 + ; CHECK: i64.const $push[[L4:.+]]=, 0 + ; CHECK: i64.store {{.*}}=, 0([[SP]]), $pop[[L4]] + store double 0.0, double* %r2 + ; CHECK: i32.const [[L4:.+]]=, 16 + ; CHECK-NEXT: i32.add [[SP]]=, [[SP]], [[L4]] + ; CHECK-NEXT: i32.const [[L5:.+]]=, __stack_pointer + ; CHECK-NEXT: i32.store [[SP]]=, 0([[L5]]), [[SP]] + ret void +} + +define void @allocarray() { + ; CHECK: i32.const [[L1:.+]]=, __stack_pointer + ; CHECK-NEXT: i32.load [[L1]]=, 0([[L1]]) + ; CHECK-NEXT: i32.const [[L2:.+]]=, 32 + ; CHECK-NEXT: i32.sub [[SP:.+]]=, [[L1]], [[L2]] + %r = alloca [5 x i32] + ; CHECK: i32.const $push[[L3:.+]]=, 1 + ; CHECK: i32.store {{.*}}=, 12([[SP]]), $pop[[L3]] + %p = getelementptr [5 x i32], [5 x i32]* %r, i32 0, i32 0 + store i32 1, i32* %p + ; CHECK: i32.const $push[[L4:.+]]=, 4 + ; CHECK: i32.const [[L5:.+]]=, 12 + ; CHECK: i32.add [[L5]]=, [[SP]], [[L5]] + ; CHECK: i32.add $push[[L6:.+]]=, [[L5]], $pop[[L4]] + ; CHECK: i32.store {{.*}}=, 0($pop[[L6]]), ${{.+}} + %p2 = getelementptr [5 x i32], [5 x i32]* %r, i32 0, i32 1 + store i32 1, i32* %p2 + ; CHECK: i32.const [[L7:.+]]=, 32 + ; CHECK-NEXT: i32.add [[SP]]=, [[SP]], [[L7]] + ; CHECK-NEXT: i32.const [[L8:.+]]=, __stack_pointer + ; CHECK-NEXT: i32.store [[SP]]=, 0([[L7]]), [[SP]] + ret void +} + +; TODO: test aligned alloc  | 

