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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-02-09 10:43:59 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-02-09 10:43:59 +0000 |
| commit | 9620f4b746c7b3b752ce5013817bd112fe5b721c (patch) | |
| tree | 38e6f96548baebc0273d56b465ccc283c10b58c8 /llvm/test | |
| parent | 873aa11dd96cf1bc67983e25095b5479eda8ac10 (diff) | |
| download | bcm5719-llvm-9620f4b746c7b3b752ce5013817bd112fe5b721c.tar.gz bcm5719-llvm-9620f4b746c7b3b752ce5013817bd112fe5b721c.zip | |
[InstCombine] Add constant vector support for X udiv C, where C >= signbit
llvm-svn: 324728
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll | 3 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/vector-udiv.ll | 10 |
2 files changed, 8 insertions, 5 deletions
diff --git a/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll b/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll index cae01558ba5..0996fd59a77 100644 --- a/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll +++ b/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll @@ -24,7 +24,8 @@ define i64 @test(i64 %X, i1 %Cond ) { define <2 x i32> @PR34856(<2 x i32> %t0, <2 x i32> %t1) { ; CHECK-LABEL: @PR34856( -; CHECK-NEXT: [[DIV1:%.*]] = udiv <2 x i32> [[T1:%.*]], <i32 -7, i32 -7> +; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i32> [[T1:%.*]], <i32 -8, i32 -8> +; CHECK-NEXT: [[DIV1:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[DIV1]] ; %cmp = icmp eq <2 x i32> %t0, <i32 1, i32 1> diff --git a/llvm/test/Transforms/InstCombine/vector-udiv.ll b/llvm/test/Transforms/InstCombine/vector-udiv.ll index 58d2fece4d7..e16c93265ba 100644 --- a/llvm/test/Transforms/InstCombine/vector-udiv.ll +++ b/llvm/test/Transforms/InstCombine/vector-udiv.ll @@ -22,8 +22,9 @@ define <4 x i32> @test_v4i32_const_pow2(<4 x i32> %a0) { ; X udiv C, where C >= signbit define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) { ; CHECK-LABEL: @test_v4i32_negconstsplat( -; CHECK-NEXT: [[TMP1:%.*]] = udiv <4 x i32> [[A0:%.*]], <i32 -3, i32 -3, i32 -3, i32 -3> -; CHECK-NEXT: ret <4 x i32> [[TMP1]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -4, i32 -4, i32 -4> +; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[TMP2]] ; %1 = udiv <4 x i32> %a0, <i32 -3, i32 -3, i32 -3, i32 -3> ret <4 x i32> %1 @@ -31,8 +32,9 @@ define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) { define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) { ; CHECK-LABEL: @test_v4i32_negconst( -; CHECK-NEXT: [[TMP1:%.*]] = udiv <4 x i32> [[A0:%.*]], <i32 -3, i32 -5, i32 -7, i32 -9> -; CHECK-NEXT: ret <4 x i32> [[TMP1]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -6, i32 -8, i32 -10> +; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[TMP2]] ; %1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9> ret <4 x i32> %1 |
