diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2016-10-15 00:58:14 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-10-15 00:58:14 +0000 |
| commit | 961811c90661390431068d9e9d222e292620e0e0 (patch) | |
| tree | f74e79c9b700aa8b3a110b486a2600cd68e2212f /llvm/test | |
| parent | 44264e1353916cbb5d447082c9e7a8ba1c56b9f3 (diff) | |
| download | bcm5719-llvm-961811c90661390431068d9e9d222e292620e0e0.tar.gz bcm5719-llvm-961811c90661390431068d9e9d222e292620e0e0.zip | |
AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25526
llvm-svn: 284298
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir | 67 |
1 files changed, 62 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir b/llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir index 9003454c358..1f283ab9483 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir @@ -1,5 +1,12 @@ # RUN: llc -march=amdgcn -run-pass post-RA-hazard-rec %s -o - | FileCheck %s +--- | + define void @div_fmas() { ret void } + define void @s_getreg() { ret void } +... +--- +# CHECK-LABEL: name: div_fmas + # CHECK-LABEL: bb.0: # CHECK: S_MOV_B64 # CHECK-NOT: S_NOP @@ -28,11 +35,7 @@ # CHECK: S_NOP # CHECK: S_NOP # CHECK: V_DIV_FMAS_F32 ---- | - define void @test0() { ret void } -... ---- -name: test0 +name: div_fmas body: | bb.0: @@ -57,4 +60,58 @@ body: | %vgpr4, %vcc = V_DIV_SCALE_F32 0, %vgpr1, 0, %vgpr1, 0, %vgpr3, 0, 0, implicit %exec %vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec S_ENDPGM + +... + +... +--- +# CHECK-LABEL: name: s_getreg + +# CHECK-LABEL: bb.0: +# CHECK: S_SETREG +# CHECK: S_NOP 0 +# CHECK: S_NOP 0 +# CHECK: S_GETREG + +# CHECK-LABEL: bb.1: +# CHECK: S_SETREG_IMM32 +# CHECK: S_NOP 0 +# CHECK: S_NOP 0 +# CHECK: S_GETREG + +# CHECK-LABEL: bb.2: +# CHECK: S_SETREG +# CHECK: S_NOP 0 +# CHECK: S_GETREG + +# CHECK-LABEL: bb.3: +# CHECK: S_SETREG +# CHECK-NEXT: S_GETREG + +name: s_getreg + +body: | + bb.0: + successors: %bb.1 + S_SETREG_B32 %sgpr0, 1 + %sgpr1 = S_GETREG_B32 1 + S_BRANCH %bb.1 + + bb.1: + successors: %bb.2 + S_SETREG_IMM32_B32 0, 1 + %sgpr1 = S_GETREG_B32 1 + S_BRANCH %bb.2 + + bb.2: + successors: %bb.3 + S_SETREG_B32 %sgpr0, 1 + %sgpr1 = S_MOV_B32 0 + %sgpr2 = S_GETREG_B32 1 + S_BRANCH %bb.3 + + bb.3: + S_SETREG_B32 %sgpr0, 0 + %sgpr1 = S_GETREG_B32 1 + S_ENDPGM ... |
