diff options
| author | Sanjay Patel <spatel@rotateright.com> | 2016-10-17 15:44:59 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-10-17 15:44:59 +0000 |
| commit | 95db75791e48852e5cfdf02236971453f43ff389 (patch) | |
| tree | 7a8d108f881e8e5a4f9063aff5048de5fe1fea56 /llvm/test | |
| parent | 832962110af1fd1ad90fa77d9631b545a8beb55d (diff) | |
| download | bcm5719-llvm-95db75791e48852e5cfdf02236971453f43ff389.tar.gz bcm5719-llvm-95db75791e48852e5cfdf02236971453f43ff389.zip | |
[x86] add tests to show missing DAG folds for arithmetic-shift-right
llvm-svn: 284394
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/sar_fold64.ll | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/sar_fold64.ll b/llvm/test/CodeGen/X86/sar_fold64.ll index cc00d2d7866..b8bd04dbb22 100644 --- a/llvm/test/CodeGen/X86/sar_fold64.ll +++ b/llvm/test/CodeGen/X86/sar_fold64.ll @@ -57,4 +57,48 @@ define i32 @shl56sar57(i64 %a) #0 { ret i32 %3 } +; FIXME + +define i8 @all_sign_bit_ashr(i8 %x) { +; CHECK-LABEL: all_sign_bit_ashr: +; CHECK: # BB#0: +; CHECK-NEXT: andb $1, %dil +; CHECK-NEXT: negb %dil +; CHECK-NEXT: sarb $6, %dil +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq +; + %and = and i8 %x, 1 + %neg = sub i8 0, %and + %sar = ashr i8 %neg, 6 + ret i8 %sar +} + +; FIXME + +define <4 x i32> @all_sign_bit_ashr_vec(<4 x i32> %x) { +; CHECK-LABEL: all_sign_bit_ashr_vec: +; CHECK: # BB#0: +; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 +; CHECK-NEXT: pxor %xmm1, %xmm1 +; CHECK-NEXT: psubd %xmm0, %xmm1 +; CHECK-NEXT: movdqa %xmm1, %xmm0 +; CHECK-NEXT: psrad $31, %xmm0 +; CHECK-NEXT: movdqa %xmm1, %xmm2 +; CHECK-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] +; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] +; CHECK-NEXT: movdqa %xmm1, %xmm0 +; CHECK-NEXT: psrad $5, %xmm0 +; CHECK-NEXT: psrad $1, %xmm1 +; CHECK-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; CHECK-NEXT: retq +; + %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> + %neg = sub <4 x i32> zeroinitializer, %and + %sar = ashr <4 x i32> %neg, <i32 1, i32 31, i32 5, i32 0> + ret <4 x i32> %sar +} + attributes #0 = { nounwind } |

