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| author | Marek Olsak <marek.olsak@amd.com> | 2016-12-09 19:49:40 +0000 |
|---|---|---|
| committer | Marek Olsak <marek.olsak@amd.com> | 2016-12-09 19:49:40 +0000 |
| commit | 91f22fbf4f5285586dfe8ca5e09a1880e82a2eb3 (patch) | |
| tree | ef2cdaff0b75042f73858032e21b795ade9c06aa /llvm/test | |
| parent | 1a4ab7e77278f0dcb827451d54a47d6d272f8282 (diff) | |
| download | bcm5719-llvm-91f22fbf4f5285586dfe8ca5e09a1880e82a2eb3.tar.gz bcm5719-llvm-91f22fbf4f5285586dfe8ca5e09a1880e82a2eb3.zip | |
AMDGPU/SI: Allow using SGPRs 96-101 on VI
Summary:
There is no point in setting SGPRS=104, because VI allocates SGPRs
in multiples of 16, so 104 -> 112. That enables us to use all 102 SGPRs
for general purposes.
Reviewers: tstellarAMD
Subscribers: qcolombet, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27149
llvm-svn: 289260
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll | 13 |
2 files changed, 8 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll b/llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll index 1cb26177ecf..d92efdc6f2d 100644 --- a/llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll @@ -76,7 +76,7 @@ define void @use_too_many_sgprs_iceland() #2 { ret void } -; ERROR: error: scalar registers limit of 102 exceeded (103) in use_too_many_sgprs_fiji +; ERROR: error: addressable scalar registers limit of 102 exceeded (103) in use_too_many_sgprs_fiji define void @use_too_many_sgprs_fiji() #3 { call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" () call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" () diff --git a/llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll b/llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll index 5d03094bb4f..e9a3a7f3fcf 100644 --- a/llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll +++ b/llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll @@ -3,8 +3,9 @@ ; Make sure this doesn't crash. ; ALL-LABEL: {{^}}test: -; ALL: s_mov_b32 s92, SCRATCH_RSRC_DWORD0 -; ALL: s_mov_b32 s91, s3 +; ALL: s_mov_b32 s[[LO:[0-9]+]], SCRATCH_RSRC_DWORD0 +; ALL: s_mov_b32 s[[OFF:[0-9]+]], s3 +; ALL: s_mov_b32 s[[HI:[0-9]+]], 0xe80000 ; Make sure we are handling hazards correctly. ; SGPR: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:12 @@ -15,11 +16,11 @@ ; Make sure scratch wave offset register is correctly incremented and ; then restored. -; SMEM: s_mov_b32 m0, s91{{$}} -; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[92:95], m0 ; 16-byte Folded Spill +; SMEM: s_mov_b32 m0, s[[OFF]]{{$}} +; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[LO]]:[[HI]]], m0 ; 16-byte Folded Spill -; SMEM: s_mov_b32 m0, s91{{$}} -; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[92:95], m0 ; 16-byte Folded Reload +; SMEM: s_mov_b32 m0, s[[OFF]]{{$}} +; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[LO]]:[[HI]]], m0 ; 16-byte Folded Reload ; SMEM: s_dcache_wb ; ALL: s_endpgm |
