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| author | Sanjay Patel <spatel@rotateright.com> | 2016-08-16 21:35:16 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-08-16 21:35:16 +0000 |
| commit | 904cd39b0562cec4a53adc02307af64189306e08 (patch) | |
| tree | 09be450af230837513486f6acfb3f07f0491d1d5 /llvm/test | |
| parent | 3044390af140b3c7a86d75aaa3b0ca7ee03432bf (diff) | |
| download | bcm5719-llvm-904cd39b0562cec4a53adc02307af64189306e08.tar.gz bcm5719-llvm-904cd39b0562cec4a53adc02307af64189306e08.zip | |
[x86] Allow merging multiple instances of an immediate within a basic block for code size savings, for 64-bit constants.
This patch handles 64-bit constants which can be encoded as 32-bit immediates.
It extends the functionality added by https://reviews.llvm.org/D11363 for 32-bit constants to 64-bit constants.
Patch by Sunita Marathe!
Differential Revision: https://reviews.llvm.org/D23391
llvm-svn: 278857
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/immediate_merging64.ll | 36 |
1 files changed, 10 insertions, 26 deletions
diff --git a/llvm/test/CodeGen/X86/immediate_merging64.ll b/llvm/test/CodeGen/X86/immediate_merging64.ll index b0d66669ba8..ea8ace12a86 100644 --- a/llvm/test/CodeGen/X86/immediate_merging64.ll +++ b/llvm/test/CodeGen/X86/immediate_merging64.ll @@ -4,36 +4,20 @@ ; Check that multiple instances of 64-bit constants encodable as ; 32-bit immediates are merged for code size savings. -@g1 = common global i64 0, align 8 -@g2 = common global i64 0, align 8 -@g3 = common global i64 0, align 8 -@g4 = common global i64 0, align 8 - ; Immediates with multiple users should not be pulled into instructions when ; optimizing for code size. -define void @imm_multiple_users(i64 %l1, i64 %l2, i64 %l3, i64 %l4) optsize { +define i1 @imm_multiple_users(i64 %a, i64* %b) optsize { ; CHECK-LABEL: imm_multiple_users: ; CHECK: # BB#0: -; CHECK-NEXT: movq $-1, {{.*}}(%rip) -; CHECK-NEXT: cmpq $-1, %rdx -; CHECK-NEXT: cmovneq %rsi, %rdi -; CHECK-NEXT: movq %rdi, {{.*}}(%rip) ; CHECK-NEXT: movq $-1, %rax -; CHECK-NEXT: # kill: %CL<def> %CL<kill> %RCX<kill> -; CHECK-NEXT: shlq %cl, %rax -; CHECK-NEXT: movq %rax, {{.*}}(%rip) -; CHECK-NEXT: movq $0, {{.*}}(%rip) +; CHECK-NEXT: movq %rax, (%rsi) +; CHECK-NEXT: cmpq %rax, %rdi +; CHECK-NEXT: sete %al ; CHECK-NEXT: retq ; - store i64 -1, i64* @g1, align 8 - %cmp = icmp eq i64 %l3, -1 - %sel = select i1 %cmp, i64 %l1, i64 %l2 - store i64 %sel, i64* @g2, align 8 - %and = and i64 %l4, 63 - %shl = shl i64 -1, %and - store i64 %shl, i64* @g3, align 8 - store i64 0, i64* @g4, align 8 - ret void + store i64 -1, i64* %b, align 8 + %cmp = icmp eq i64 %a, -1 + ret i1 %cmp } declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) @@ -44,11 +28,11 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) define void @memset_zero(i8* noalias nocapture %D) optsize { ; CHECK-LABEL: memset_zero: ; CHECK: # BB#0: -; CHECK-NEXT: movq $0, 7(%rdi) -; CHECK-NEXT: movq $0, (%rdi) +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movq %rax, 7(%rdi) +; CHECK-NEXT: movq %rax, (%rdi) ; CHECK-NEXT: retq ; tail call void @llvm.memset.p0i8.i64(i8* %D, i8 0, i64 15, i32 1, i1 false) ret void } - |
