[mips][FastISel] Implement srem/urem and sdiv/udiv instructions.

Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel.

Based on a patch by Reed Kotler.

Test Plan:
srem1.ll
div1.ll
test-suite at O0/O2 for mips32 r1/r2

Reviewers: dsanders, rkotler

Subscribers: llvm-commits, rfuhler

Differential Revision: http://reviews.llvm.org/D7028

llvm-svn: 238757

2 files changed, 111 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll
new file mode 100644
index 00000000000..89e7f211251
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
+; RUN:      -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
+; RUN:      -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s
+
+@sj = global i32 200000, align 4
+@sk = global i32 -47, align 4
+@uj = global i32 200000, align 4
+@uk = global i32 43, align 4
+@si = common global i32 0, align 4
+@ui = common global i32 0, align 4
+
+define void @divs() {
+  ; CHECK-LABEL:  divs:
+
+  ; CHECK:        lui     $[[GOT1:[0-9]+]], %hi(_gp_disp)
+  ; CHECK:        addiu   $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
+  ; CHECK:        addu    $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
+  ; CHECK-DAG:    lw      $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])
+  ; CHECK-DAG:    lw      $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])
+  ; CHECK-DAG:    lw      $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])
+  ; CHECK-DAG:    lw      $[[J:[0-9]+]], 0($[[J_ADDR]])
+  ; CHECK-DAG:    lw      $[[K:[0-9]+]], 0($[[K_ADDR]])
+  ; CHECK-DAG:    div     $zero, $[[J]], $[[K]]
+  ; CHECK_DAG:    teq     $[[K]], $zero, 7
+  ; CHECK-DAG:    mflo    $[[RESULT:[0-9]+]]
+  ; CHECK:        sw      $[[RESULT]], 0($[[I_ADDR]])
+  %1 = load i32, i32* @sj, align 4
+  %2 = load i32, i32* @sk, align 4
+  %div = sdiv i32 %1, %2
+  store i32 %div, i32* @si, align 4
+  ret void
+}
+
+define void @divu() {
+  ; CHECK-LABEL:  divu:
+
+  ; CHECK:            lui     $[[GOT1:[0-9]+]], %hi(_gp_disp)
+  ; CHECK:            addiu   $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
+  ; CHECK:            addu    $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
+  ; CHECK-DAG:        lw      $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])
+  ; CHECK-DAG:        lw      $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])
+  ; CHECK-DAG:        lw      $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])
+  ; CHECK-DAG:        lw      $[[J:[0-9]+]], 0($[[J_ADDR]])
+  ; CHECK-DAG:        lw      $[[K:[0-9]+]], 0($[[K_ADDR]])
+  ; CHECK-DAG:        divu    $zero, $[[J]], $[[K]]
+  ; CHECK_DAG:        teq     $[[K]], $zero, 7
+  ; CHECK-DAG:        mflo    $[[RESULT:[0-9]+]]
+  ; CHECK:            sw      $[[RESULT]], 0($[[I_ADDR]])
+  %1 = load i32, i32* @uj, align 4
+  %2 = load i32, i32* @uk, align 4
+  %div = udiv i32 %1, %2
+  store i32 %div, i32* @ui, align 4
+  ret void
+}
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll
new file mode 100644
index 00000000000..9b5e440d0ea
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
+; RUN:      -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
+; RUN:      -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s
+
+@sj = global i32 200, align 4
+@sk = global i32 -47, align 4
+@uj = global i32 200, align 4
+@uk = global i32 43, align 4
+@si = common global i32 0, align 4
+@ui = common global i32 0, align 4
+
+define void @rems() {
+  ; CHECK-LABEL:  rems:
+
+  ; CHECK:            lui     $[[GOT1:[0-9]+]], %hi(_gp_disp)
+  ; CHECK:            addiu   $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
+  ; CHECK:            addu    $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
+  ; CHECK-DAG:        lw      $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])
+  ; CHECK-DAG:        lw      $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])
+  ; CHECK-DAG:        lw      $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])
+  ; CHECK-DAG:        lw      $[[J:[0-9]+]], 0($[[J_ADDR]])
+  ; CHECK-DAG:        lw      $[[K:[0-9]+]], 0($[[K_ADDR]])
+  ; CHECK-DAG:        div     $zero, $[[J]], $[[K]]
+  ; CHECK_DAG:        teq     $[[K]], $zero, 7
+  ; CHECK-DAG:        mfhi    $[[RESULT:[0-9]+]]
+  ; CHECK:            sw      $[[RESULT]], 0($[[I_ADDR]])
+  %1 = load i32, i32* @sj, align 4
+  %2 = load i32, i32* @sk, align 4
+  %rem = srem i32 %1, %2
+  store i32 %rem, i32* @si, align 4
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @remu() {
+  ; CHECK-LABEL:  remu:
+
+  ; CHECK:            lui     $[[GOT1:[0-9]+]], %hi(_gp_disp)
+  ; CHECK:            addiu   $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
+  ; CHECK:            addu    $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
+  ; CHECK-DAG:        lw      $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])
+  ; CHECK-DAG:        lw      $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])
+  ; CHECK-DAG:        lw      $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])
+  ; CHECK-DAG:        lw      $[[J:[0-9]+]], 0($[[J_ADDR]])
+  ; CHECK-DAG:        lw      $[[K:[0-9]+]], 0($[[K_ADDR]])
+  ; CHECK-DAG:        divu    $zero, $[[J]], $[[K]]
+  ; CHECK_DAG:        teq     $[[K]], $zero, 7
+  ; CHECK-DAG:        mfhi    $[[RESULT:[0-9]+]]
+  ; CHECK:            sw      $[[RESULT]], 0($[[I_ADDR]])
+  %1 = load i32, i32* @uj, align 4
+  %2 = load i32, i32* @uk, align 4
+  %rem = urem i32 %1, %2
+  store i32 %rem, i32* @ui, align 4
+  ret void
+}