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| author | Jyotsna Verma <jverma@codeaurora.org> | 2013-04-23 19:15:55 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-04-23 19:15:55 +0000 |
| commit | 89c84821eab88641143fef1c1f8f8bab1b3a55f6 (patch) | |
| tree | a843fe0960c10f580ee97d4637a45c7a1cf34b06 /llvm/test | |
| parent | 03fa38aa5b2b5b5ed60fbead35b0b76dc57dfb14 (diff) | |
| download | bcm5719-llvm-89c84821eab88641143fef1c1f8f8bab1b3a55f6.tar.gz bcm5719-llvm-89c84821eab88641143fef1c1f8f8bab1b3a55f6.zip | |
Hexagon: Remove assembler mapped instruction definitions.
llvm-svn: 180133
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/cmp_pred2.ll | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/cmp_pred2.ll b/llvm/test/CodeGen/Hexagon/cmp_pred2.ll new file mode 100644 index 00000000000..a20b9f09b6e --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/cmp_pred2.ll @@ -0,0 +1,87 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; Make sure that the assembler mapped compare instructions are correctly generated. + +@c = common global i32 0, align 4 + +define i32 @test1(i32 %a, i32 %b) nounwind { +; CHECK-NOT: cmp.ge +; CHECK: cmp.gt +entry: + %cmp = icmp slt i32 %a, 100 + br i1 %cmp, label %if.then, label %entry.if.end_crit_edge + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add nsw i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} + +define i32 @test2(i32 %a, i32 %b) nounwind { +; CHECK-NOT: cmp.lt +; CHECK: cmp.gt +entry: + %cmp = icmp sge i32 %a, %b + br i1 %cmp, label %entry.if.end_crit_edge, label %if.then + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add nsw i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} + +define i32 @test4(i32 %a, i32 %b) nounwind { +; CHECK-NOT: cmp.ltu +; CHECK: cmp.gtu +entry: + %cmp = icmp uge i32 %a, %b + br i1 %cmp, label %entry.if.end_crit_edge, label %if.then + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} + +define i32 @test5(i32 %a, i32 %b) nounwind { +; CHECK: cmp.gtu +entry: + %cmp = icmp uge i32 %a, 29999 + br i1 %cmp, label %if.then, label %entry.if.end_crit_edge + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} |

