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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-26 20:39:42 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-26 20:39:42 +0000 |
| commit | 894e53d6ac00a54adecb2b3b1d3a68ef88929c88 (patch) | |
| tree | fba6a5e78e55544d9aeef7b918dcc26016d802a7 /llvm/test | |
| parent | ca7e6f6ea843800c03965950b66ef1da4c1aee7f (diff) | |
| download | bcm5719-llvm-894e53d6ac00a54adecb2b3b1d3a68ef88929c88.tar.gz bcm5719-llvm-894e53d6ac00a54adecb2b3b1d3a68ef88929c88.zip | |
AMDGPU: Fix using SMRD instructions for argument loads in functions
These are not actually uniform values except in kernels.
llvm-svn: 309172
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/hsa-func.ll | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-func.ll b/llvm/test/CodeGen/AMDGPU/hsa-func.ll index 35aeeeaa225..0bf1c6a23c3 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-func.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-func.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA-CI %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA-VI %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj | llvm-readobj -symbols -s -sd | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF @@ -27,7 +27,7 @@ ; ELF: Symbol { ; ELF: Name: simple -; ELF: Size: 48 +; ELF: Size: 36 ; ELF: Type: Function (0x2) ; ELF: } @@ -41,12 +41,9 @@ ; HSA: .p2align 2 ; HSA: {{^}}simple: ; HSA-NOT: amd_kernel_code_t -; HSA-NOT: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 +; HSA: flat_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[0:1] ; Make sure we are setting the ATC bit: -; HSA-CI: s_mov_b32 s[[HI:[0-9]+]], 0x100f000 -; On VI+ we also need to set MTYPE = 2 -; HSA-VI: s_mov_b32 s[[HI:[0-9]+]], 0x1100f000 ; Make sure we generate flat store for HSA ; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} |
