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| author | Craig Topper <craig.topper@intel.com> | 2018-03-29 20:41:39 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-29 20:41:39 +0000 |
| commit | 89310f56c80cbf277cd0edc8cbdda864f64c82d8 (patch) | |
| tree | ab036f31ecf23f5e4f2bd658623bd87fa09b2489 /llvm/test | |
| parent | 5c14ed89f606155089150783fc5e6ddce36c836b (diff) | |
| download | bcm5719-llvm-89310f56c80cbf277cd0edc8cbdda864f64c82d8.tar.gz bcm5719-llvm-89310f56c80cbf277cd0edc8cbdda864f64c82d8.zip | |
[X86] Correct the placement of ReadAfterLd in BEXTR and BZHI. Add dedicated SchedRW for BEXTR/BZHI.
These instructions have the memory operand before the register operand. So we need to put ReadDefault for all the load ops first. Then the ReadAfterLd
Differential Revision: https://reviews.llvm.org/D44838
llvm-svn: 328823
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/bmi-schedule.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/bmi2-schedule.ll | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/X86/bmi-schedule.ll b/llvm/test/CodeGen/X86/bmi-schedule.ll index e38bf5ddd39..d5ab1cf5f50 100644 --- a/llvm/test/CodeGen/X86/bmi-schedule.ll +++ b/llvm/test/CodeGen/X86/bmi-schedule.ll @@ -172,8 +172,8 @@ define i64 @test_andn_i64(i64 %a0, i64 %a1, i64 *%a2) { define i32 @test_bextr_i32(i32 %a0, i32 %a1, i32 *%a2) { ; GENERIC-LABEL: test_bextr_i32: ; GENERIC: # %bb.0: -; GENERIC-NEXT: bextrl %edi, (%rdx), %ecx # sched: [5:0.50] -; GENERIC-NEXT: bextrl %edi, %esi, %eax # sched: [1:0.33] +; GENERIC-NEXT: bextrl %edi, (%rdx), %ecx # sched: [6:1.00] +; GENERIC-NEXT: bextrl %edi, %esi, %eax # sched: [2:1.00] ; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -222,8 +222,8 @@ declare i32 @llvm.x86.bmi.bextr.32(i32, i32) define i64 @test_bextr_i64(i64 %a0, i64 %a1, i64 *%a2) { ; GENERIC-LABEL: test_bextr_i64: ; GENERIC: # %bb.0: -; GENERIC-NEXT: bextrq %rdi, (%rdx), %rcx # sched: [5:0.50] -; GENERIC-NEXT: bextrq %rdi, %rsi, %rax # sched: [1:0.33] +; GENERIC-NEXT: bextrq %rdi, (%rdx), %rcx # sched: [6:1.00] +; GENERIC-NEXT: bextrq %rdi, %rsi, %rax # sched: [2:1.00] ; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; diff --git a/llvm/test/CodeGen/X86/bmi2-schedule.ll b/llvm/test/CodeGen/X86/bmi2-schedule.ll index 1ccd7c394f7..0a79b661e2a 100644 --- a/llvm/test/CodeGen/X86/bmi2-schedule.ll +++ b/llvm/test/CodeGen/X86/bmi2-schedule.ll @@ -9,8 +9,8 @@ define i32 @test_bzhi_i32(i32 %a0, i32 %a1, i32 *%a2) { ; GENERIC-LABEL: test_bzhi_i32: ; GENERIC: # %bb.0: -; GENERIC-NEXT: bzhil %edi, (%rdx), %ecx # sched: [5:0.50] -; GENERIC-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.33] +; GENERIC-NEXT: bzhil %edi, (%rdx), %ecx # sched: [5:1.00] +; GENERIC-NEXT: bzhil %edi, %esi, %eax # sched: [1:1.00] ; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -59,8 +59,8 @@ declare i32 @llvm.x86.bmi.bzhi.32(i32, i32) define i64 @test_bzhi_i64(i64 %a0, i64 %a1, i64 *%a2) { ; GENERIC-LABEL: test_bzhi_i64: ; GENERIC: # %bb.0: -; GENERIC-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [5:0.50] -; GENERIC-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.33] +; GENERIC-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [5:1.00] +; GENERIC-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:1.00] ; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; |
