[AArch64][SVE] Asm: Support for FEXPA and FTSSEL.

This patch adds support for transcendental acceleration
instructions 'FEXPA' (exponential accelerator) and 'FTSSEL'
(trigonometric select coefficient).

llvm-svn: 338121

4 files changed, 73 insertions, 0 deletions

diff --git a/llvm/test/MC/AArch64/SVE/fexpa-diagnostics.s b/llvm/test/MC/AArch64/SVE/fexpa-diagnostics.s
new file mode 100644
index 00000000000..2269ae0fdfc
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fexpa-diagnostics.s
@@ -0,0 +1,15 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+fexpa z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fexpa z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fexpa z0.s, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fexpa z0.s, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fexpa.s b/llvm/test/MC/AArch64/SVE/fexpa.s
new file mode 100644
index 00000000000..503af1ef80a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fexpa.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fexpa z0.h, z31.h
+// CHECK-INST: fexpa	z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0xbb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bb 60 04 <unknown>
+
+fexpa z0.s, z31.s
+// CHECK-INST: fexpa	z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0xbb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bb a0 04 <unknown>
+
+fexpa z0.d, z31.d
+// CHECK-INST: fexpa	z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0xbb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bb e0 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ftssel-diagnostics.s b/llvm/test/MC/AArch64/SVE/ftssel-diagnostics.s
new file mode 100644
index 00000000000..92991246163
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ftssel-diagnostics.s
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+ftssel    z0.b, z1.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ftssel    z0.b, z1.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/ftssel.s b/llvm/test/MC/AArch64/SVE/ftssel.s
new file mode 100644
index 00000000000..3e9ec71a554
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ftssel.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ftssel    z0.h, z1.h, z31.h
+// CHECK-INST: ftssel	z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xb0,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 b0 7f 04 <unknown>
+
+ftssel    z0.s, z1.s, z31.s
+// CHECK-INST: ftssel	z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xb0,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 b0 bf 04 <unknown>
+
+ftssel    z0.d, z1.d, z31.d
+// CHECK-INST: ftssel	z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xb0,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 b0 ff 04 <unknown>