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author | Chris Lattner <sabre@nondot.org> | 2009-09-27 07:56:52 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2009-09-27 07:56:52 +0000 |
commit | 8879e06d0acf8eab30ce8c0d8f1fc75058f25605 (patch) | |
tree | 8343515cb4b4dafa397433e7020fa4c388131f56 /llvm/test | |
parent | 14d1cccc2be9ecde362183a50d4d15c169e0c813 (diff) | |
download | bcm5719-llvm-8879e06d0acf8eab30ce8c0d8f1fc75058f25605.tar.gz bcm5719-llvm-8879e06d0acf8eab30ce8c0d8f1fc75058f25605.zip |
implement and document support for filecheck variables. This
allows matching and remembering a string and then matching and
verifying that the string occurs later in the file.
Change X86/xor.ll to use this in some cases where the test was
checking for an arbitrary register allocation decision.
llvm-svn: 82891
Diffstat (limited to 'llvm/test')
-rw-r--r-- | llvm/test/CodeGen/X86/xor.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/X86/xor.ll b/llvm/test/CodeGen/X86/xor.ll index af263f95b8d..7bd06bba4c3 100644 --- a/llvm/test/CodeGen/X86/xor.ll +++ b/llvm/test/CodeGen/X86/xor.ll @@ -58,11 +58,11 @@ bb12: ret i32 %tmp3 ; X64: test4: -; X64: notl %eax -; X64: andl {{.*}}%eax +; X64: notl [[REG:%[a-z]+]] +; X64: andl {{.*}}[[REG]] ; X32: test4: -; X32: notl %edx -; X32: andl {{.*}}%edx +; X32: notl [[REG:%[a-z]+]] +; X32: andl {{.*}}[[REG]] } define i16 @test5(i16 %a, i16 %b) nounwind { @@ -80,11 +80,11 @@ bb: bb12: ret i16 %tmp3 ; X64: test5: -; X64: notw %ax -; X64: andw {{.*}}%ax +; X64: notw [[REG:%[a-z]+]] +; X64: andw {{.*}}[[REG]] ; X32: test5: -; X32: notw %dx -; X32: andw {{.*}}%dx +; X32: notw [[REG:%[a-z]+]] +; X32: andw {{.*}}[[REG]] } define i8 @test6(i8 %a, i8 %b) nounwind { @@ -102,11 +102,11 @@ bb: bb12: ret i8 %tmp3 ; X64: test6: -; X64: notb %al -; X64: andb {{.*}}%al +; X64: notb [[REG:%[a-z]+]] +; X64: andb {{.*}}[[REG]] ; X32: test6: -; X32: notb %dl -; X32: andb {{.*}}%dl +; X32: notb [[REG:%[a-z]+]] +; X32: andb {{.*}}[[REG]] } define i32 @test7(i32 %a, i32 %b) nounwind { @@ -124,10 +124,10 @@ bb: bb12: ret i32 %tmp3 ; X64: test7: -; X64: xorl $2147483646, %eax -; X64: andl {{.*}}%eax +; X64: xorl $2147483646, [[REG:%[a-z]+]] +; X64: andl {{.*}}[[REG]] ; X32: test7: -; X32: xorl $2147483646, %edx -; X32: andl {{.*}}%edx +; X32: xorl $2147483646, [[REG:%[a-z]+]] +; X32: andl {{.*}}[[REG]] } |