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authorNirav Dave <niravd@google.com>2017-04-18 15:36:34 +0000
committerNirav Dave <niravd@google.com>2017-04-18 15:36:34 +0000
commit855ef456026078574fa2cbeec728fa6acb79cc55 (patch)
tree01a9bc308a51966caf0bd81fe80771ef68c83b65 /llvm/test
parent47fd10c3b530c8b7ef262335279486aecf83cb6c (diff)
downloadbcm5719-llvm-855ef456026078574fa2cbeec728fa6acb79cc55.tar.gz
bcm5719-llvm-855ef456026078574fa2cbeec728fa6acb79cc55.zip
[DAG] Improve store merge candidate pruning.
Remove non-consecutive stores from store merge candidate search as they cannot be merged and will prevent us from finding subsequent mergeable store cases. Reviewers: jyknight, bogner, javed.absar, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32086 llvm-svn: 300561
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-abi.ll4
-rw-r--r--llvm/test/CodeGen/X86/MergeConsecutiveStores.ll12
2 files changed, 4 insertions, 12 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-abi.ll b/llvm/test/CodeGen/AArch64/arm64-abi.ll
index 6cf0ab35b9b..5be84b7d493 100644
--- a/llvm/test/CodeGen/AArch64/arm64-abi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-abi.ll
@@ -43,9 +43,7 @@ entry:
; CHECK-LABEL: i8i16caller
; The 8th, 9th, 10th and 11th arguments are passed at sp, sp+2, sp+4, sp+5.
; They are i8, i16, i8 and i8.
-; CHECK-DAG: strb {{w[0-9]+}}, [sp, #5]
-; CHECK-DAG: strb {{w[0-9]+}}, [sp, #4]
-; CHECK-DAG: strh {{w[0-9]+}}, [sp, #2]
+; CHECK-DAG: stur {{w[0-9]+}}, [sp, #2]
; CHECK-DAG: strb {{w[0-9]+}}, [sp]
; CHECK: bl
; FAST-LABEL: i8i16caller
diff --git a/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll b/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll
index 906ca2fef68..f89f6e1de1a 100644
--- a/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll
+++ b/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll
@@ -596,14 +596,8 @@ define void @almost_consecutive_stores(i8* %p) {
store i8 3, i8* %p3
ret void
; CHECK-LABEL: almost_consecutive_stores
-; CHECK-DAG: movb $0, (%rdi)
-; CHECK-DAG: movb $1, 42(%rdi)
-; CHECK-DAG: movb $2, 2(%rdi)
-; CHECK-DAG: movb $3, 3(%rdi)
+; CHECK-DAG: movb $0, (%rdi)
+; CHECK-DAG: movb $1, 42(%rdi)
+; CHECK-DAG: movw $770, 2(%rdi)
; CHECK: retq
-
-; We should able to merge the final two stores into a 16-bit store
-; FIXMECHECK-DAG: movw $770, 2(%rdi)
-
-
}
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