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| author | Evan Cheng <evan.cheng@apple.com> | 2012-03-06 23:33:32 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2012-03-06 23:33:32 +0000 |
| commit | 80893ce5f517f416d96313b74d416adfd41aaf08 (patch) | |
| tree | 6cbd22f941848f5db1ef862a1d58cd6579cf0704 /llvm/test | |
| parent | 297e69f15e501efdbcb8063ab25496144742cd89 (diff) | |
| download | bcm5719-llvm-80893ce5f517f416d96313b74d416adfd41aaf08.tar.gz bcm5719-llvm-80893ce5f517f416d96313b74d416adfd41aaf08.zip | |
Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).
llvm-svn: 152162
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/shifter_operand.ll | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll index 521ffa1c9e3..eb971ff72e7 100644 --- a/llvm/test/CodeGen/ARM/shifter_operand.ll +++ b/llvm/test/CodeGen/ARM/shifter_operand.ll @@ -54,12 +54,16 @@ declare i8* @malloc(...) define fastcc void @test4(i16 %addr) nounwind { entry: ; A8: test4: -; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A8: str [[REG]], [r0] +; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! +; A8: str [[REG]], [r0, r1, lsl #2] +; A8-NOT: str [[REG]], [r0] ; A9: test4: -; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A9: str [[REG]], [r0] +; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! +; A9: str [[REG]], [r0, r1, lsl #2] +; A9-NOT: str [[REG]], [r0] %0 = tail call i8* (...)* @malloc(i32 undef) nounwind %1 = bitcast i8* %0 to i32* %2 = sext i16 %addr to i32 |
