summaryrefslogtreecommitdiffstats
path: root/llvm/test
diff options
context:
space:
mode:
authorSaleem Abdulrasool <compnerd@compnerd.org>2016-11-06 19:46:54 +0000
committerSaleem Abdulrasool <compnerd@compnerd.org>2016-11-06 19:46:54 +0000
commit804e12eeb5db92e47ef696d064d596f923f481c9 (patch)
tree9cd55e36f6a71351523ee077b9825bd5ff41af32 /llvm/test
parentf8d38d11b9323d875b85623193940b117c1ec4fa (diff)
downloadbcm5719-llvm-804e12eeb5db92e47ef696d064d596f923f481c9.tar.gz
bcm5719-llvm-804e12eeb5db92e47ef696d064d596f923f481c9.zip
ARM: lower fpowi appropriately for Windows ARM
This handles the last case of the builtin function calls that we would generate code which differed from Microsoft's ABI. Rather than generating a call to `__pow{d,s}i2` we now promote the parameter to a float or double and invoke `powf` or `pow` instead. Addresses PR30825! llvm-svn: 286082
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/ARM/Windows/powi.ll57
1 files changed, 57 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/Windows/powi.ll b/llvm/test/CodeGen/ARM/Windows/powi.ll
new file mode 100644
index 00000000000..4ec4b0abbdf
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/Windows/powi.ll
@@ -0,0 +1,57 @@
+; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s
+
+declare double @llvm.powi.f64(double, i32)
+declare float @llvm.powi.f32(float, i32)
+
+define arm_aapcs_vfpcc double @d(double %d, i32 %i) {
+entry:
+ %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
+ ret double %0
+}
+
+; CHECK-LABEL: d:
+; CHECK: vmov s[[REGISTER:[0-9]+]], r0
+; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
+; CHECK-NEXT: b pow
+; CHECK-NOT: __powisf2
+
+define arm_aapcs_vfpcc float @f(float %f, i32 %i) {
+entry:
+ %0 = tail call float @llvm.powi.f32(float %f, i32 %i)
+ ret float %0
+}
+
+; CHECK-LABEL: f:
+; CHECK: vmov s[[REGISTER:[0-9]+]], r0
+; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
+; CHECK-NEXT: b pow
+; CHECK-NOT: __powisf2
+
+define arm_aapcs_vfpcc float @g(double %d, i32 %i) {
+entry:
+ %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
+ %conv = fptrunc double %0 to float
+ ret float %conv
+}
+
+; CHECK-LABEL: g:
+; CHECK: vmov s[[REGISTER:[0-9]+]], r0
+; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
+; CHECK-NEXT: bl pow
+; CHECK-NOT: bl __powidf2
+; CHECK-NEXT: vcvt.f32.f64 s0, d0
+
+define arm_aapcs_vfpcc double @h(float %f, i32 %i) {
+entry:
+ %0 = tail call float @llvm.powi.f32(float %f, i32 %i)
+ %conv = fpext float %0 to double
+ ret double %conv
+}
+
+; CHECK-LABEL: h:
+; CHECK: vmov s[[REGISTER:[0-9]+]], r0
+; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
+; CHECK-NEXT: bl powf
+; CHECK-NOT: bl __powisf2
+; CHECK-NEXT: vcvt.f64.f32 d0, s0
+
OpenPOWER on IntegriCloud