[AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.

The variants added by this patch are:
- SQINC     signed increment, e.g. sqinc x0, w0, all, mul #4
- SQDEC     signed decrement, e.g. sqdec x0, w0, all, mul #4
- UQINC   unsigned increment, e.g. uqinc w0, all, mul #4
- UQDEC   unsigned decrement, e.g. uqdec w0, all, mul #4
 
This patch includes asmparser changes to parse a GPR64 as a GPR32 in
order to satisfy the constraint check:
  x0 == GPR64(w0)
in:
  sqinc x0, w0, all, mul #4
         ^___^ (must match)

Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D47716

llvm-svn: 334980

32 files changed, 920 insertions, 40 deletions

diff --git a/llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s
index 92527fe068a..84bd1e23a8c 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s
@@ -20,6 +20,20 @@ sqdecb sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqdecb x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqdecb x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecb x0, x1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecb x0, x1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqdecb x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/sqdecb.s b/llvm/test/MC/AArch64/SVE/sqdecb.s
index 4cb6da9b8e7..570c3331e07 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecb.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecb.s
@@ -37,6 +37,47 @@ sqdecb  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdecb  x0, w0
+// CHECK-INST: sqdecb  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
+
+sqdecb  x0, w0, all
+// CHECK-INST: sqdecb  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
+
+sqdecb  x0, w0, all, mul #1
+// CHECK-INST: sqdecb  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
+
+sqdecb  x0, w0, all, mul #16
+// CHECK-INST: sqdecb  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 2f 04 <unknown>
+
+sqdecb  x0, w0, pow2
+// CHECK-INST: sqdecb  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 20 04 <unknown>
+
+sqdecb  x0, w0, pow2, mul #16
+// CHECK-INST: sqdecb  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf8,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 2f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s
index 46b43a31bb8..2b7f89900ce 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s
@@ -20,6 +20,20 @@ sqdecd sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqdecd x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqdecd x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecd x0, x1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecd x0, x1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqdecd x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/sqdecd.s b/llvm/test/MC/AArch64/SVE/sqdecd.s
index 00338533c1c..a5b9a72e3f1 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecd.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecd.s
@@ -37,6 +37,47 @@ sqdecd  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdecd  x0, w0
+// CHECK-INST: sqdecd  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
+
+sqdecd  x0, w0, all
+// CHECK-INST: sqdecd  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
+
+sqdecd  x0, w0, all, mul #1
+// CHECK-INST: sqdecd  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
+
+sqdecd  x0, w0, all, mul #16
+// CHECK-INST: sqdecd  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb ef 04 <unknown>
+
+sqdecd  x0, w0, pow2
+// CHECK-INST: sqdecd  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 e0 04 <unknown>
+
+sqdecd  x0, w0, pow2, mul #16
+// CHECK-INST: sqdecd  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf8,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/sqdech-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqdech-diagnostics.s
index b85cd699cbd..385dad9bd26 100644
--- a/llvm/test/MC/AArch64/SVE/sqdech-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/sqdech-diagnostics.s
@@ -20,6 +20,20 @@ sqdech sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqdech x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqdech x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdech x0, x1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdech x0, x1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqdech x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/sqdech.s b/llvm/test/MC/AArch64/SVE/sqdech.s
index c58599a6938..d6e52a85c5c 100644
--- a/llvm/test/MC/AArch64/SVE/sqdech.s
+++ b/llvm/test/MC/AArch64/SVE/sqdech.s
@@ -37,6 +37,47 @@ sqdech  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdech  x0, w0
+// CHECK-INST: sqdech  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
+
+sqdech  x0, w0, all
+// CHECK-INST: sqdech  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
+
+sqdech  x0, w0, all, mul #1
+// CHECK-INST: sqdech  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
+
+sqdech  x0, w0, all, mul #16
+// CHECK-INST: sqdech  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb 6f 04 <unknown>
+
+sqdech  x0, w0, pow2
+// CHECK-INST: sqdech  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 60 04 <unknown>
+
+sqdech  x0, w0, pow2, mul #16
+// CHECK-INST: sqdech  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf8,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/sqdecw-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqdecw-diagnostics.s
index bfea93b4be4..48a9751d05d 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecw-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecw-diagnostics.s
@@ -20,6 +20,20 @@ sqdecw sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqdecw x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqdecw x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecw x0, x1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqdecw x0, x1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqdecw x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/sqdecw.s b/llvm/test/MC/AArch64/SVE/sqdecw.s
index 26c5ef90df6..07706d80079 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecw.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecw.s
@@ -37,6 +37,47 @@ sqdecw  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqdecw  x0, w0
+// CHECK-INST: sqdecw  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
+
+sqdecw  x0, w0, all
+// CHECK-INST: sqdecw  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
+
+sqdecw  x0, w0, all, mul #1
+// CHECK-INST: sqdecw  x0, w0
+// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
+
+sqdecw  x0, w0, all, mul #16
+// CHECK-INST: sqdecw  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xfb,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 fb af 04 <unknown>
+
+sqdecw  x0, w0, pow2
+// CHECK-INST: sqdecw  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf8,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 a0 04 <unknown>
+
+sqdecw  x0, w0, pow2, mul #16
+// CHECK-INST: sqdecw  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf8,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f8 af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/sqincb-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqincb-diagnostics.s
index 3c16c3538ee..4d6d3e5d7b2 100644
--- a/llvm/test/MC/AArch64/SVE/sqincb-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/sqincb-diagnostics.s
@@ -20,6 +20,20 @@ sqincb sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqincb x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqincb x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincb x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincb x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqincb x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/sqincb.s b/llvm/test/MC/AArch64/SVE/sqincb.s
index 5d261a0a948..8a3d3566b0a 100644
--- a/llvm/test/MC/AArch64/SVE/sqincb.s
+++ b/llvm/test/MC/AArch64/SVE/sqincb.s
@@ -37,6 +37,47 @@ sqincb  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqincb  x0, w0
+// CHECK-INST: sqincb  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
+
+sqincb  x0, w0, all
+// CHECK-INST: sqincb  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
+
+sqincb  x0, w0, all, mul #1
+// CHECK-INST: sqincb  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
+
+sqincb  x0, w0, all, mul #16
+// CHECK-INST: sqincb  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 2f 04 <unknown>
+
+sqincb  x0, w0, pow2
+// CHECK-INST: sqincb  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 20 04 <unknown>
+
+sqincb  x0, w0, pow2, mul #16
+// CHECK-INST: sqincb  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf0,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 2f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/sqincd-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqincd-diagnostics.s
index a6f382a78d9..c43d019a879 100644
--- a/llvm/test/MC/AArch64/SVE/sqincd-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/sqincd-diagnostics.s
@@ -20,6 +20,20 @@ sqincd sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqincd x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqincd x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincd x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincd x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqincd x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/sqincd.s b/llvm/test/MC/AArch64/SVE/sqincd.s
index 37a4e335032..c74d6978c1f 100644
--- a/llvm/test/MC/AArch64/SVE/sqincd.s
+++ b/llvm/test/MC/AArch64/SVE/sqincd.s
@@ -37,6 +37,47 @@ sqincd  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqincd  x0, w0
+// CHECK-INST: sqincd  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
+
+sqincd  x0, w0, all
+// CHECK-INST: sqincd  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
+
+sqincd  x0, w0, all, mul #1
+// CHECK-INST: sqincd  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
+
+sqincd  x0, w0, all, mul #16
+// CHECK-INST: sqincd  x0, w0, all
+// CHECK-ENCODING: [0xe0,0xf3,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 ef 04 <unknown>
+
+sqincd  x0, w0, pow2
+// CHECK-INST: sqincd  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 e0 04 <unknown>
+
+sqincd  x0, w0, pow2, mul #16
+// CHECK-INST: sqincd  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf0,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/sqinch-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqinch-diagnostics.s
index 368fd4c60e6..d926d28a188 100644
--- a/llvm/test/MC/AArch64/SVE/sqinch-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/sqinch-diagnostics.s
@@ -20,6 +20,20 @@ sqinch sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqinch x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqinch x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqinch x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqinch x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqinch x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/sqinch.s b/llvm/test/MC/AArch64/SVE/sqinch.s
index a19dcee6949..fd4befdbef0 100644
--- a/llvm/test/MC/AArch64/SVE/sqinch.s
+++ b/llvm/test/MC/AArch64/SVE/sqinch.s
@@ -37,6 +37,47 @@ sqinch  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqinch  x0, w0
+// CHECK-INST: sqinch  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
+
+sqinch  x0, w0, all
+// CHECK-INST: sqinch  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
+
+sqinch  x0, w0, all, mul #1
+// CHECK-INST: sqinch  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
+
+sqinch  x0, w0, all, mul #16
+// CHECK-INST: sqinch  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 6f 04 <unknown>
+
+sqinch  x0, w0, pow2
+// CHECK-INST: sqinch  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 60 04 <unknown>
+
+sqinch  x0, w0, pow2, mul #16
+// CHECK-INST: sqinch  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf0,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/sqincw-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqincw-diagnostics.s
index ab768d0cdde..7f9f1857ff8 100644
--- a/llvm/test/MC/AArch64/SVE/sqincw-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/sqincw-diagnostics.s
@@ -20,6 +20,20 @@ sqincw sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up
+
+sqincw x0, w1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
+// CHECK-NEXT: sqincw x0, w1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincw x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: sqincw x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 sqincw x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/sqincw.s b/llvm/test/MC/AArch64/SVE/sqincw.s
index cc7e6d2e996..d21b16756bd 100644
--- a/llvm/test/MC/AArch64/SVE/sqincw.s
+++ b/llvm/test/MC/AArch64/SVE/sqincw.s
@@ -37,6 +37,47 @@ sqincw  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (x0, w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+sqincw  x0, w0
+// CHECK-INST: sqincw  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
+
+sqincw  x0, w0, all
+// CHECK-INST: sqincw  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
+
+sqincw  x0, w0, all, mul #1
+// CHECK-INST: sqincw  x0, w0
+// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
+
+sqincw  x0, w0, all, mul #16
+// CHECK-INST: sqincw  x0, w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f3 af 04 <unknown>
+
+sqincw  x0, w0, pow2
+// CHECK-INST: sqincw  x0, w0, pow2
+// CHECK-ENCODING: [0x00,0xf0,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 a0 04 <unknown>
+
+sqincw  x0, w0, pow2, mul #16
+// CHECK-INST: sqincw  x0, w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf0,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/uqdecb-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqdecb-diagnostics.s
index 002f30a6a4b..e817451f886 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecb-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecb-diagnostics.s
@@ -3,11 +3,6 @@
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqdecb w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqdecb w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqdecb wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdecb wsp
@@ -20,6 +15,25 @@ uqdecb sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned dec only has one register operand)
+
+uqdecb x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecb x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecb x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqdecb x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/uqdecb.s b/llvm/test/MC/AArch64/SVE/uqdecb.s
index 6fe639c8a8f..4b4e0664fc1 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecb.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecb.s
@@ -37,6 +37,47 @@ uqdecb  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqdecb  w0
+// CHECK-INST: uqdecb  w0
+// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
+
+uqdecb  w0, all
+// CHECK-INST: uqdecb  w0
+// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
+
+uqdecb  w0, all, mul #1
+// CHECK-INST: uqdecb  w0
+// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
+
+uqdecb  w0, all, mul #16
+// CHECK-INST: uqdecb  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 2f 04 <unknown>
+
+uqdecb  w0, pow2
+// CHECK-INST: uqdecb  w0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 20 04 <unknown>
+
+uqdecb  w0, pow2, mul #16
+// CHECK-INST: uqdecb  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xfc,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 2f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/uqdecd-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqdecd-diagnostics.s
index 5e39897def5..e2f626eb013 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecd-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecd-diagnostics.s
@@ -3,11 +3,6 @@
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqdecd w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqdecd w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqdecd wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdecd wsp
@@ -20,6 +15,25 @@ uqdecd sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned dec only has one register operand)
+
+uqdecd x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecd x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecd x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqdecd x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/uqdecd.s b/llvm/test/MC/AArch64/SVE/uqdecd.s
index fe5c6d24d93..ce8208cd6bf 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecd.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecd.s
@@ -37,6 +37,47 @@ uqdecd  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqdecd  w0
+// CHECK-INST: uqdecd  w0
+// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
+
+uqdecd  w0, all
+// CHECK-INST: uqdecd  w0
+// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
+
+uqdecd  w0, all, mul #1
+// CHECK-INST: uqdecd  w0
+// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
+
+uqdecd  w0, all, mul #16
+// CHECK-INST: uqdecd  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff ef 04 <unknown>
+
+uqdecd  w0, pow2
+// CHECK-INST: uqdecd  w0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc e0 04 <unknown>
+
+uqdecd  w0, pow2, mul #16
+// CHECK-INST: uqdecd  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xfc,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/uqdech-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqdech-diagnostics.s
index 26e415bd5a7..50fd50e6dbe 100644
--- a/llvm/test/MC/AArch64/SVE/uqdech-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/uqdech-diagnostics.s
@@ -3,11 +3,6 @@
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqdech w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqdech w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqdech wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdech wsp
@@ -20,6 +15,25 @@ uqdech sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned dec only has one register operand)
+
+uqdech x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdech x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdech x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqdech x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/uqdech.s b/llvm/test/MC/AArch64/SVE/uqdech.s
index d751813ea12..5a3a63bcfd3 100644
--- a/llvm/test/MC/AArch64/SVE/uqdech.s
+++ b/llvm/test/MC/AArch64/SVE/uqdech.s
@@ -37,6 +37,47 @@ uqdech  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqdech  w0
+// CHECK-INST: uqdech  w0
+// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
+
+uqdech  w0, all
+// CHECK-INST: uqdech  w0
+// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
+
+uqdech  w0, all, mul #1
+// CHECK-INST: uqdech  w0
+// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
+
+uqdech  w0, all, mul #16
+// CHECK-INST: uqdech  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff 6f 04 <unknown>
+
+uqdech  w0, pow2
+// CHECK-INST: uqdech  w0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 60 04 <unknown>
+
+uqdech  w0, pow2, mul #16
+// CHECK-INST: uqdech  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xfc,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/uqdecw-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqdecw-diagnostics.s
index 56b6298138d..0dd7b0d07f2 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecw-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecw-diagnostics.s
@@ -3,11 +3,6 @@
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqdecw w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqdecw w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqdecw wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqdecw wsp
@@ -20,6 +15,25 @@ uqdecw sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned dec only has one register operand)
+
+uqdecw x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecw x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqdecw x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqdecw x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/uqdecw.s b/llvm/test/MC/AArch64/SVE/uqdecw.s
index d4c168c0db9..61330702cd8 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecw.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecw.s
@@ -37,6 +37,47 @@ uqdecw  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqdecw  w0
+// CHECK-INST: uqdecw  w0
+// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
+
+uqdecw  w0, all
+// CHECK-INST: uqdecw  w0
+// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
+
+uqdecw  w0, all, mul #1
+// CHECK-INST: uqdecw  w0
+// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
+
+uqdecw  w0, all, mul #16
+// CHECK-INST: uqdecw  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xff,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 ff af 04 <unknown>
+
+uqdecw  w0, pow2
+// CHECK-INST: uqdecw  w0, pow2
+// CHECK-ENCODING: [0x00,0xfc,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc a0 04 <unknown>
+
+uqdecw  w0, pow2, mul #16
+// CHECK-INST: uqdecw  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xfc,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 fc af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/uqincb-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqincb-diagnostics.s
index a6fd75c2d24..22346933b19 100644
--- a/llvm/test/MC/AArch64/SVE/uqincb-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/uqincb-diagnostics.s
@@ -3,11 +3,6 @@
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqincb w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqincb w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqincb wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqincb wsp
@@ -20,6 +15,25 @@ uqincb sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned inc only has one register operand)
+
+uqincb x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincb x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincb x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqincb x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/uqincb.s b/llvm/test/MC/AArch64/SVE/uqincb.s
index f3529d388c4..16c621c512a 100644
--- a/llvm/test/MC/AArch64/SVE/uqincb.s
+++ b/llvm/test/MC/AArch64/SVE/uqincb.s
@@ -37,6 +37,47 @@ uqincb  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqincb  w0
+// CHECK-INST: uqincb  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
+
+uqincb  w0, all
+// CHECK-INST: uqincb  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
+
+uqincb  w0, all, mul #1
+// CHECK-INST: uqincb  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
+
+uqincb  w0, all, mul #16
+// CHECK-INST: uqincb  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 2f 04 <unknown>
+
+uqincb  w0, pow2
+// CHECK-INST: uqincb  w0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 20 04 <unknown>
+
+uqincb  w0, pow2, mul #16
+// CHECK-INST: uqincb  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf4,0x2f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 2f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/uqincd-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqincd-diagnostics.s
index a234c7b5882..12f36dc6c97 100644
--- a/llvm/test/MC/AArch64/SVE/uqincd-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/uqincd-diagnostics.s
@@ -3,11 +3,6 @@
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqincd w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqincd w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqincd wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqincd wsp
@@ -20,6 +15,25 @@ uqincd sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned inc only has one register operand)
+
+uqincd x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincd x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincd x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqincd x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/uqincd.s b/llvm/test/MC/AArch64/SVE/uqincd.s
index 4823f489f04..fccfbadc5a5 100644
--- a/llvm/test/MC/AArch64/SVE/uqincd.s
+++ b/llvm/test/MC/AArch64/SVE/uqincd.s
@@ -37,6 +37,47 @@ uqincd  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqincd  w0
+// CHECK-INST: uqincd  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
+
+uqincd  w0, all
+// CHECK-INST: uqincd  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
+
+uqincd  w0, all, mul #1
+// CHECK-INST: uqincd  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
+
+uqincd  w0, all, mul #16
+// CHECK-INST: uqincd  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 ef 04 <unknown>
+
+uqincd  w0, pow2
+// CHECK-INST: uqincd  w0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 e0 04 <unknown>
+
+uqincd  w0, pow2, mul #16
+// CHECK-INST: uqincd  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf4,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/uqinch-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqinch-diagnostics.s
index 995ae22a7c5..ba22906d8d6 100644
--- a/llvm/test/MC/AArch64/SVE/uqinch-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/uqinch-diagnostics.s
@@ -3,11 +3,6 @@
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqinch w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqinch w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqinch wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqinch wsp
@@ -20,6 +15,25 @@ uqinch sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned inc only has one register operand)
+
+uqinch x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqinch x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqinch x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqinch x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/uqinch.s b/llvm/test/MC/AArch64/SVE/uqinch.s
index 5bffa14d6f4..26f76431f8a 100644
--- a/llvm/test/MC/AArch64/SVE/uqinch.s
+++ b/llvm/test/MC/AArch64/SVE/uqinch.s
@@ -37,6 +37,47 @@ uqinch  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqinch  w0
+// CHECK-INST: uqinch  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
+
+uqinch  w0, all
+// CHECK-INST: uqinch  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
+
+uqinch  w0, all, mul #1
+// CHECK-INST: uqinch  w0
+// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
+
+uqinch  w0, all, mul #16
+// CHECK-INST: uqinch  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 6f 04 <unknown>
+
+uqinch  w0, pow2
+// CHECK-INST: uqinch  w0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 60 04 <unknown>
+
+uqinch  w0, pow2, mul #16
+// CHECK-INST: uqinch  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf4,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//
 
diff --git a/llvm/test/MC/AArch64/SVE/uqincw-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqincw-diagnostics.s
index 6a770d203ea..629dcf1d662 100644
--- a/llvm/test/MC/AArch64/SVE/uqincw-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/uqincw-diagnostics.s
@@ -3,11 +3,6 @@
 // ------------------------------------------------------------------------- //
 // Invalid result register
 
-uqincw w0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
-// CHECK-NEXT: uqincw w0
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
 uqincw wsp
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: uqincw wsp
@@ -20,6 +15,25 @@ uqincw sp
 
 
 // ------------------------------------------------------------------------- //
+// Operands not matching up (unsigned inc only has one register operand)
+
+uqincw x0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw x0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw w0, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw w0, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincw x0, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
+// CHECK-NEXT: uqincw x0, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.
 
 uqincw x0, all, mul #-1
diff --git a/llvm/test/MC/AArch64/SVE/uqincw.s b/llvm/test/MC/AArch64/SVE/uqincw.s
index 8bd35d1c4e5..1c6d9a88b0e 100644
--- a/llvm/test/MC/AArch64/SVE/uqincw.s
+++ b/llvm/test/MC/AArch64/SVE/uqincw.s
@@ -37,6 +37,47 @@ uqincw  x0, all, mul #16
 
 
 // ---------------------------------------------------------------------------//
+// Test 32-bit form (w0) and its aliases
+// ---------------------------------------------------------------------------//
+
+uqincw  w0
+// CHECK-INST: uqincw  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
+
+uqincw  w0, all
+// CHECK-INST: uqincw  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
+
+uqincw  w0, all, mul #1
+// CHECK-INST: uqincw  w0
+// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
+
+uqincw  w0, all, mul #16
+// CHECK-INST: uqincw  w0, all, mul #16
+// CHECK-ENCODING: [0xe0,0xf7,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 f7 af 04 <unknown>
+
+uqincw  w0, pow2
+// CHECK-INST: uqincw  w0, pow2
+// CHECK-ENCODING: [0x00,0xf4,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 a0 04 <unknown>
+
+uqincw  w0, pow2, mul #16
+// CHECK-INST: uqincw  w0, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xf4,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f4 af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//