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| author | Eric Christopher <echristo@apple.com> | 2011-07-08 00:04:56 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2011-07-08 00:04:56 +0000 |
| commit | 7a2a0f80de2b1a0994b85e23cb5d01c384135474 (patch) | |
| tree | 352283663fc57501457f7634907a1b3ac23e2e2a /llvm/test | |
| parent | 3aa229f7dca58676e2a4f143387fb0b53e2b783d (diff) | |
| download | bcm5719-llvm-7a2a0f80de2b1a0994b85e23cb5d01c384135474.tar.gz bcm5719-llvm-7a2a0f80de2b1a0994b85e23cb5d01c384135474.zip | |
Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.
Fixes PR9675 and rdar://9740801
llvm-svn: 134664
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/membarrier.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/membarrier.ll b/llvm/test/CodeGen/X86/membarrier.ll new file mode 100644 index 00000000000..42f8ef5ff04 --- /dev/null +++ b/llvm/test/CodeGen/X86/membarrier.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=x86-64 -mattr=-sse -O0 +; PR9675 + +define i32 @t() { +entry: + %i = alloca i32, align 4 + store i32 1, i32* %i, align 4 + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + %0 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %i, i32 1) + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + ret i32 0 +} + +declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind |
