AMDGCN/SI: Implement readlane/readfirstlane intrinsics

Summary:
  This patch implements readlane/readfirstlane intrinsics.
TODO: need to define a new register class to consider the case
that the source could be a vector register or M0.

Reviewed by:
  arsenm and tstellarAMD

Differential Revision:
  http://reviews.llvm.org/D22489

llvm-svn: 279660

2 files changed, 78 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
new file mode 100644
index 00000000000..09732ff0f60
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
@@ -0,0 +1,35 @@
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
+
+declare i32 @llvm.amdgcn.readfirstlane(i32) #0
+
+; CHECK-LABEL: {{^}}test_readfirstlane:
+; CHECK: v_readfirstlane_b32 s{{[0-9]+}}, v{{[0-9]+}}
+define void @test_readfirstlane(i32 addrspace(1)* %out, i32 %src) #1 {
+  %readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %src)
+  store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; CHECK-LABEL: {{^}}test_readfirstlane_imm:
+; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], 32
+; CHECK: v_readfirstlane_b32 s{{[0-9]+}}, [[VVAL]]
+define void @test_readfirstlane_imm(i32 addrspace(1)* %out) #1 {
+  %readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 32)
+  store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; TODO: m0 should be folded.
+; CHECK-LABEL: {{^}}test_readfirstlane_m0:
+; CHECK: s_mov_b32 m0, -1
+; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], m0
+; CHECK: v_readfirstlane_b32 s{{[0-9]+}}, [[VVAL]]
+define void @test_readfirstlane_m0(i32 addrspace(1)* %out) #1 {
+  %m0 = call i32 asm "s_mov_b32 m0, -1", "={M0}"()
+  %readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %m0)
+  store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+attributes #0 = { nounwind readnone convergent }
+attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
new file mode 100644
index 00000000000..923cd725f82
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
@@ -0,0 +1,43 @@
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
+
+declare i32 @llvm.amdgcn.readlane(i32, i32) #0
+
+; CHECK-LABEL: {{^}}test_readlane_sreg:
+; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
+define void @test_readlane_sreg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
+  %readlane = call i32 @llvm.amdgcn.readlane(i32 %src0, i32 %src1)
+  store i32 %readlane, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; CHECK-LABEL: {{^}}test_readlane_imm_sreg:
+; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], 32
+; CHECK: v_readlane_b32 s{{[0-9]+}}, [[VVAL]], s{{[0-9]+}}
+define void @test_readlane_imm_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
+  %readlane = call i32 @llvm.amdgcn.readlane(i32 32, i32 %src1)
+  store i32 %readlane, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; TODO: m0 should be folded.
+; CHECK-LABEL: {{^}}test_readlane_m0_sreg:
+; CHECK: s_mov_b32 m0, -1
+; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], m0
+; CHECK: v_readlane_b32 s{{[0-9]+}}, [[VVAL]], s{{[0-9]+}}
+define void @test_readlane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
+  %m0 = call i32 asm "s_mov_b32 m0, -1", "={M0}"()
+  %readlane = call i32 @llvm.amdgcn.readlane(i32 %m0, i32 %src1)
+  store i32 %readlane, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; CHECK-LABEL: {{^}}test_readlane_imm:
+; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 32
+define void @test_readlane_imm(i32 addrspace(1)* %out, i32 %src0) #1 {
+  %readlane = call i32 @llvm.amdgcn.readlane(i32 %src0, i32 32) #0
+  store i32 %readlane, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+attributes #0 = { nounwind readnone convergent }
+attributes #1 = { nounwind }