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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2017-09-01 16:56:32 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2017-09-01 16:56:32 +0000 |
| commit | 75c98c365b8b4c42e9ba84351b0aef8f73f69019 (patch) | |
| tree | 8ba286e66c7f88b0380430c668f22de4251b4041 /llvm/test | |
| parent | 0b94bfc70985fb7952646113bbaff388f4dfdd72 (diff) | |
| download | bcm5719-llvm-75c98c365b8b4c42e9ba84351b0aef8f73f69019.tar.gz bcm5719-llvm-75c98c365b8b4c42e9ba84351b0aef8f73f69019.zip | |
AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states
Summary:
This fixes a bug that was exposed on gfx9 in various
GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests,
e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment
Reviewers: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D36193
llvm-svn: 312337
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/hazard.mir | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/hazard.mir b/llvm/test/CodeGen/AMDGPU/hazard.mir new file mode 100644 index 00000000000..d495a327e9e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/hazard.mir @@ -0,0 +1,31 @@ +# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s +# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s + +# GCN: bb.0.entry: +# GCN: %m0 = S_MOV_B32 +# GFX9: S_NOP 0 +# VI-NOT: S_NOP_0 +# GCN: V_INTERP_P1_F32 + +--- +name: hazard_implicit_def +alignment: 0 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: +liveins: + - { reg: '%sgpr7', virtual-reg: '' } + - { reg: '%vgpr4', virtual-reg: '' } +body: | + bb.0.entry: + liveins: %sgpr7, %vgpr4 + + %m0 = S_MOV_B32 killed %sgpr7 + %vgpr5 = IMPLICIT_DEF + %vgpr0 = V_INTERP_P1_F32 killed %vgpr4, 0, 0, implicit %m0, implicit %exec + SI_RETURN_TO_EPILOG killed %vgpr5, killed %vgpr0 + +... |
