diff options
| author | Joel Jones <joelkevinjones@gmail.com> | 2016-11-30 22:25:24 +0000 |
|---|---|---|
| committer | Joel Jones <joelkevinjones@gmail.com> | 2016-11-30 22:25:24 +0000 |
| commit | 75818bc8f76b317ae79fdf69428ee6a2e1630fb2 (patch) | |
| tree | 64ae800d7fe3680e889c2ca424eb3b305532ea3b /llvm/test | |
| parent | 0c4300fac7e011c5b3072a005a68c4f8ce2e639f (diff) | |
| download | bcm5719-llvm-75818bc8f76b317ae79fdf69428ee6a2e1630fb2.tar.gz bcm5719-llvm-75818bc8f76b317ae79fdf69428ee6a2e1630fb2.zip | |
[AArch64] Refactor LSE support as feature separate from V8.1a support.
Summary:
This is preparation for ThunderX processors that have Large
System Extension (LSE) atomic instructions, but not the
other instructions introduced by V8.1a.
This will mimic changes to GCC as described here:
https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00388.html
LSE instructions are: LD/ST<op>, CAS*, SWP
Reviewers: t.p.northover, echristo, jmolloy, rengolin
Subscribers: aemerson, mehdi_amini
Differential Revision: https://reviews.llvm.org/D26621
llvm-svn: 288279
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/AArch64/arm64v8.1-diagno-predicate.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/directive-arch-negative.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/directive-cpu.s | 11 |
3 files changed, 25 insertions, 0 deletions
diff --git a/llvm/test/MC/AArch64/arm64v8.1-diagno-predicate.s b/llvm/test/MC/AArch64/arm64v8.1-diagno-predicate.s new file mode 100644 index 00000000000..9540d295c8f --- /dev/null +++ b/llvm/test/MC/AArch64/arm64v8.1-diagno-predicate.s @@ -0,0 +1,8 @@ +// RUN: not llvm-mc -triple=arm64-linux-gnu -mattr=armv8.1a -mattr=-lse < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s + + casa w5, w7, [x20] +// CHECK-ERROR: error: instruction requires: lse +// CHECK-ERROR-NEXT: casa w5, w7, [x20] +// CHECK-ERROR-NEXT: ^ + diff --git a/llvm/test/MC/AArch64/directive-arch-negative.s b/llvm/test/MC/AArch64/directive-arch-negative.s index 327389de024..43ccd792725 100644 --- a/llvm/test/MC/AArch64/directive-arch-negative.s +++ b/llvm/test/MC/AArch64/directive-arch-negative.s @@ -35,3 +35,9 @@ # CHECK: error: instruction requires: ras # CHECK: esb + + .arch armv8.1-a+nolse + casa w5, w7, [x20] + +# CHECK: error: instruction requires: lse +# CHECK: casa w5, w7, [x20] diff --git a/llvm/test/MC/AArch64/directive-cpu.s b/llvm/test/MC/AArch64/directive-cpu.s index 8e7d4533744..d645e54e470 100644 --- a/llvm/test/MC/AArch64/directive-cpu.s +++ b/llvm/test/MC/AArch64/directive-cpu.s @@ -36,6 +36,12 @@ aesd v0.16b, v2.16b + .cpu generic+v8.1a+nolse + casa w5, w7, [x20] + + .cpu generic+v8.1a+lse + casa w5, w7, [x20] + // NOTE: the errors precede the actual output! The errors appear in order // though, so validate by hoisting them to the top and preservering relative // ordering @@ -56,8 +62,13 @@ // CHECK: aesd v0.16b, v2.16b // CHECK: ^ +// CHECK: error: instruction requires: lse +// CHECK: casa w5, w7, [x20] +// CHECK: ^ + // CHECK: fminnm d0, d0, d1 // CHECK: fminnm d0, d0, d1 // CHECK: addp v0.4s, v0.4s, v0.4s // CHECK: crc32cx w0, w1, x3 // CHECK: aesd v0.16b, v2.16b +// CHECK: casa w5, w7, [x20] |
