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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-12-15 17:09:24 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-12-15 17:09:24 +0000 |
| commit | 7522f54feb3baf9cf347ba48fdf7923981206743 (patch) | |
| tree | b979f1fd34dbd6e84c2cd6c1184e353b5b96cc85 /llvm/test | |
| parent | 6ea759a83eb4b3dabf1d5c310386d1e44069e283 (diff) | |
| download | bcm5719-llvm-7522f54feb3baf9cf347ba48fdf7923981206743.tar.gz bcm5719-llvm-7522f54feb3baf9cf347ba48fdf7923981206743.zip | |
[X86][SSE] Fix domains for scalar store instructions
As discussed on D27692
llvm-svn: 289834
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/masked_memop.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/oddshuffles.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_ins_extract-1.ll | 8 |
3 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/X86/masked_memop.ll b/llvm/test/CodeGen/X86/masked_memop.ll index 7e1837c42a9..f3b3d933982 100644 --- a/llvm/test/CodeGen/X86/masked_memop.ll +++ b/llvm/test/CodeGen/X86/masked_memop.ll @@ -979,12 +979,12 @@ define void @test21(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) { define void @one_mask_bit_set1(<4 x i32>* %addr, <4 x i32> %val) { ; AVX-LABEL: one_mask_bit_set1: ; AVX: ## BB#0: -; AVX-NEXT: vmovd %xmm0, (%rdi) +; AVX-NEXT: vmovss %xmm0, (%rdi) ; AVX-NEXT: retq ; ; AVX512-LABEL: one_mask_bit_set1: ; AVX512: ## BB#0: -; AVX512-NEXT: vmovd %xmm0, (%rdi) +; AVX512-NEXT: vmovss %xmm0, (%rdi) ; AVX512-NEXT: retq call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 false, i1 false, i1 false>) ret void diff --git a/llvm/test/CodeGen/X86/oddshuffles.ll b/llvm/test/CodeGen/X86/oddshuffles.ll index 89d5c4eb1e4..48869f186fe 100644 --- a/llvm/test/CodeGen/X86/oddshuffles.ll +++ b/llvm/test/CodeGen/X86/oddshuffles.ll @@ -359,7 +359,7 @@ define void @v7i32(<4 x i32> %a, <4 x i32> %b, <7 x i32>* %p) nounwind { ; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm2[0,2,3,2] ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3] ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,0,3] -; AVX1-NEXT: vmovd %xmm1, 24(%rdi) +; AVX1-NEXT: vmovss %xmm1, 24(%rdi) ; AVX1-NEXT: vmovlps %xmm0, 16(%rdi) ; AVX1-NEXT: vmovaps %xmm2, (%rdi) ; AVX1-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_ins_extract-1.ll b/llvm/test/CodeGen/X86/vec_ins_extract-1.ll index 8adc0e61f8a..85c7875d923 100644 --- a/llvm/test/CodeGen/X86/vec_ins_extract-1.ll +++ b/llvm/test/CodeGen/X86/vec_ins_extract-1.ll @@ -90,8 +90,8 @@ define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind { ; X32-NEXT: movl %esp, %ebp ; X32-NEXT: andl $-16, %esp ; X32-NEXT: subl $32, %esp -; X32-NEXT: movdqa %xmm0, (%esp) -; X32-NEXT: movd %xmm0, (%esp,%eax,4) +; X32-NEXT: movaps %xmm0, (%esp) +; X32-NEXT: movss %xmm0, (%esp,%eax,4) ; X32-NEXT: movaps (%esp), %xmm0 ; X32-NEXT: movl %ebp, %esp ; X32-NEXT: popl %ebp @@ -99,9 +99,9 @@ define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind { ; ; X64-LABEL: t3: ; X64: # BB#0: -; X64-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) +; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; X64-NEXT: movslq %edi, %rax -; X64-NEXT: movd %xmm0, -24(%rsp,%rax,4) +; X64-NEXT: movss %xmm0, -24(%rsp,%rax,4) ; X64-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0 ; X64-NEXT: retq %t9 = extractelement <4 x i32> %t8, i32 0 |
