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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-15 14:42:36 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-15 14:42:36 +0000 |
| commit | 750082d1fe306405c6b3350ce84c4b9c446eb5c3 (patch) | |
| tree | 5d0dd93610a7757e648a6b75af9ca3abbd7e1550 /llvm/test | |
| parent | 38c67a27fe811074d39aaba6d4e9fbcc8f0640fc (diff) | |
| download | bcm5719-llvm-750082d1fe306405c6b3350ce84c4b9c446eb5c3.tar.gz bcm5719-llvm-750082d1fe306405c6b3350ce84c4b9c446eb5c3.zip | |
AMDGPU/SI: Fix regression with no-return atomics
Summary:
In the added test-case, the atomic instruction feeds into a non-machine
CopyToReg node which hasn't been selected yet, so guard against
non-machine opcodes here.
Reviewers: arsenm, tstellarAMD
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D19043
llvm-svn: 266433
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll index 458ef78da18..1d848726533 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll @@ -100,6 +100,15 @@ main_body: ret float %out } +;CHECK-LABEL: {{^}}test4: +;CHECK: buffer_atomic_add v0, +define amdgpu_ps float @test4() { +main_body: + %v = call i32 @llvm.amdgcn.buffer.atomic.add(i32 1, <4 x i32> undef, i32 0, i32 4, i1 false) + %v.float = bitcast i32 %v to float + ret float %v.float +} + declare i32 @llvm.amdgcn.buffer.atomic.swap(i32, <4 x i32>, i32, i32, i1) #0 declare i32 @llvm.amdgcn.buffer.atomic.add(i32, <4 x i32>, i32, i32, i1) #0 declare i32 @llvm.amdgcn.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i1) #0 |
