diff options
| author | Wei Ding <wei.ding2@amd.com> | 2016-08-11 20:34:48 +0000 |
|---|---|---|
| committer | Wei Ding <wei.ding2@amd.com> | 2016-08-11 20:34:48 +0000 |
| commit | 70cda07526b8bcfef4766bdf104d79ae2ad222d8 (patch) | |
| tree | da11cc2e165291f812af433fe0164e0a5c076f41 /llvm/test | |
| parent | 3ab5816000a8e0daaa4798981132551239025454 (diff) | |
| download | bcm5719-llvm-70cda07526b8bcfef4766bdf104d79ae2ad222d8.tar.gz bcm5719-llvm-70cda07526b8bcfef4766bdf104d79ae2ad222d8.zip | |
AMDGPU : Add intrinsic for instruction v_cvt_pk_u8_f32
Differential Revision: http://reviews.llvm.org/D23336
llvm-svn: 278403
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll b/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll new file mode 100644 index 00000000000..9246ce38dbe --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll @@ -0,0 +1,60 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare i32 @llvm.amdgcn.cvt.pk.u8.f32(float, i32, i32) #0 + +; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx_0: +; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 0, v{{[0-9]+}} +define void @v_cvt_pk_u8_f32_idx_0(i32 addrspace(1)* %out, float %src, i32 %reg) { + %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 0, i32 %reg) #0 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx_1: +; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 1, v{{[0-9]+}} +define void @v_cvt_pk_u8_f32_idx_1(i32 addrspace(1)* %out, float %src, i32 %reg) { + %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 1, i32 %reg) #0 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx_2: +; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 2, v{{[0-9]+}} +define void @v_cvt_pk_u8_f32_idx_2(i32 addrspace(1)* %out, float %src, i32 %reg) { + %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 2, i32 %reg) #0 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx_3: +; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 3, v{{[0-9]+}} +define void @v_cvt_pk_u8_f32_idx_3(i32 addrspace(1)* %out, float %src, i32 %reg) { + %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 3, i32 %reg) #0 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_combine: +; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 0, v{{[0-9]+}} +; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 1, v{{[0-9]+}} +; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 2, v{{[0-9]+}} +; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 3, v{{[0-9]+}} +define void @v_cvt_pk_u8_f32_combine(i32 addrspace(1)* %out, float %src, i32 %reg) { + %result0 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 0, i32 %reg) #0 + %result1 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 1, i32 %result0) #0 + %result2 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 2, i32 %result1) #0 + %result3 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 3, i32 %result2) #0 + store i32 %result3, i32 addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx: +; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @v_cvt_pk_u8_f32_idx(i32 addrspace(1)* %out, float %src, i32 %idx, i32 %reg) { + %result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 %idx, i32 %reg) #0 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind readnone } |
