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| author | Tim Northover <tnorthover@apple.com> | 2014-04-03 13:06:54 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-03 13:06:54 +0000 |
| commit | 70450c59a4b3212e72892c6932b7e77eeeaea086 (patch) | |
| tree | 14a35c5353a437786cf772ea287bd8a49149787b /llvm/test | |
| parent | 425314a65f753c029be35dfd7ede0533b6b99f44 (diff) | |
| download | bcm5719-llvm-70450c59a4b3212e72892c6932b7e77eeeaea086.tar.gz bcm5719-llvm-70450c59a4b3212e72892c6932b7e77eeeaea086.zip | |
ARM: skip cmpxchg failure barrier if ordering is monotonic.
The terminal barrier of a cmpxchg expansion will be either Acquire or
SequentiallyConsistent. In either case it can be skipped if the
operation has Monotonic requirements on failure.
rdar://problem/15996804
llvm-svn: 205535
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-op.ll | 37 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-ops-v8.ll | 7 |
2 files changed, 41 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/ARM/atomic-op.ll b/llvm/test/CodeGen/ARM/atomic-op.ll index 9a79c9fd7b1..ac8e949cf18 100644 --- a/llvm/test/CodeGen/ARM/atomic-op.ll +++ b/llvm/test/CodeGen/ARM/atomic-op.ll @@ -194,3 +194,40 @@ entry: %0 = atomicrmw add i32* %p, i32 1 monotonic ret i32 %0 } + +define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) { +; CHECK-LABEL: test_cmpxchg_fail_order: + + %oldval = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic +; CHECK: dmb ish +; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]: +; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]] +; CHECK: cmp [[OLDVAL]], r1 +; CHECK: bxne lr +; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]] +; CHECK: cmp [[SUCCESS]], #0 +; CHECK: bne [[LOOP_BB]] +; CHECK: dmb ish +; CHECK: bx lr + + ret i32 %oldval +} + +define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) { +; CHECK-LABEL: test_cmpxchg_fail_order1: + + %oldval = cmpxchg i32* %addr, i32 %desired, i32 %new acquire acquire +; CHECK-NOT: dmb ish +; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]: +; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]] +; CHECK: cmp [[OLDVAL]], r1 +; CHECK: bne [[END_BB:\.?LBB[0-9]+_[0-9]+]] +; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]] +; CHECK: cmp [[SUCCESS]], #0 +; CHECK: bne [[LOOP_BB]] +; CHECK: [[END_BB]]: +; CHECK: dmb ish +; CHECK: bx lr + + ret i32 %oldval +} diff --git a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll index 1ca78bfd1e3..00f9006c155 100644 --- a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll +++ b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll @@ -1075,9 +1075,10 @@ define i16 @test_atomic_cmpxchg_i16(i16 zeroext %wanted, i16 zeroext %new) nounw ret i16 %old } -define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { +define void @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; CHECK-LABEL: test_atomic_cmpxchg_i32: %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release monotonic + store i32 %old, i32* @var32 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 @@ -1097,8 +1098,8 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD]] - ret i32 %old +; CHECK: str{{(.w)?}} r[[OLD]], + ret void } define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { |
