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| author | Craig Topper <craig.topper@intel.com> | 2017-10-04 17:20:12 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-04 17:20:12 +0000 |
| commit | 6fb55716e9c77e716f4ac25abc84687eac29f848 (patch) | |
| tree | 07097be59b5b39b860012ae8d20d8248fb9a6506 /llvm/test | |
| parent | 5a09996ff70ee0cd533c8d401f3924aee662551f (diff) | |
| download | bcm5719-llvm-6fb55716e9c77e716f4ac25abc84687eac29f848.tar.gz bcm5719-llvm-6fb55716e9c77e716f4ac25abc84687eac29f848.zip | |
[X86] Redefine MOVSS/MOVSD instructions to take VR128 regclass as input instead of FR32/FR64
This patch redefines the MOVSS/MOVSD instructions to take VR128 as its second input. This allows the MOVSS/SD->BLEND commute to work without requiring a COPY to be inserted.
This should fix PR33079
Overall this looks to be an improvement in the generated code. I haven't checked the EXPENSIVE_CHECKS build but I'll do that and update with results.
Differential Revision: https://reviews.llvm.org/D38449
llvm-svn: 314914
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/buildvec-insertvec.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/lower-vec-shift.ll | 56 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/psubus.ll | 171 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-blend.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-compare-results.ll | 260 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-rotate-128.ll | 120 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 140 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shift-lshr-128.ll | 92 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shift-shl-128.ll | 28 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-trunc-math.ll | 207 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-trunc.ll | 60 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vshift-4.ll | 20 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/x86-shifts.ll | 4 |
13 files changed, 562 insertions, 602 deletions
diff --git a/llvm/test/CodeGen/X86/buildvec-insertvec.ll b/llvm/test/CodeGen/X86/buildvec-insertvec.ll index 3d7a221d50a..5c508b24f95 100644 --- a/llvm/test/CodeGen/X86/buildvec-insertvec.ll +++ b/llvm/test/CodeGen/X86/buildvec-insertvec.ll @@ -39,10 +39,10 @@ define <4 x float> @test_negative_zero_1(<4 x float> %A) { ; SSE2: # BB#0: # %entry ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] -; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero -; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] +; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/lower-vec-shift.ll b/llvm/test/CodeGen/X86/lower-vec-shift.ll index 8d64baf5f2a..936de7c761a 100644 --- a/llvm/test/CodeGen/X86/lower-vec-shift.ll +++ b/llvm/test/CodeGen/X86/lower-vec-shift.ll @@ -12,10 +12,9 @@ define <8 x i16> @test1(<8 x i16> %a) { ; SSE-LABEL: test1: ; SSE: # BB#0: ; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrlw $2, %xmm1 -; SSE-NEXT: psrlw $3, %xmm0 -; SSE-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] -; SSE-NEXT: movaps %xmm1, %xmm0 +; SSE-NEXT: psrlw $3, %xmm1 +; SSE-NEXT: psrlw $2, %xmm0 +; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE-NEXT: retq ; ; AVX1-LABEL: test1: @@ -39,10 +38,9 @@ define <8 x i16> @test2(<8 x i16> %a) { ; SSE-LABEL: test2: ; SSE: # BB#0: ; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrlw $2, %xmm1 -; SSE-NEXT: psrlw $3, %xmm0 -; SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; SSE-NEXT: movapd %xmm1, %xmm0 +; SSE-NEXT: psrlw $3, %xmm1 +; SSE-NEXT: psrlw $2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSE-NEXT: retq ; ; AVX1-LABEL: test2: @@ -66,10 +64,9 @@ define <4 x i32> @test3(<4 x i32> %a) { ; SSE-LABEL: test3: ; SSE: # BB#0: ; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrld $2, %xmm1 -; SSE-NEXT: psrld $3, %xmm0 -; SSE-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] -; SSE-NEXT: movaps %xmm1, %xmm0 +; SSE-NEXT: psrld $3, %xmm1 +; SSE-NEXT: psrld $2, %xmm0 +; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE-NEXT: retq ; ; AVX1-LABEL: test3: @@ -91,10 +88,9 @@ define <4 x i32> @test4(<4 x i32> %a) { ; SSE-LABEL: test4: ; SSE: # BB#0: ; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrld $2, %xmm1 -; SSE-NEXT: psrld $3, %xmm0 -; SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; SSE-NEXT: movapd %xmm1, %xmm0 +; SSE-NEXT: psrld $3, %xmm1 +; SSE-NEXT: psrld $2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSE-NEXT: retq ; ; AVX1-LABEL: test4: @@ -116,10 +112,9 @@ define <8 x i16> @test5(<8 x i16> %a) { ; SSE-LABEL: test5: ; SSE: # BB#0: ; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psraw $2, %xmm1 -; SSE-NEXT: psraw $3, %xmm0 -; SSE-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] -; SSE-NEXT: movaps %xmm1, %xmm0 +; SSE-NEXT: psraw $3, %xmm1 +; SSE-NEXT: psraw $2, %xmm0 +; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE-NEXT: retq ; ; AVX1-LABEL: test5: @@ -143,10 +138,9 @@ define <8 x i16> @test6(<8 x i16> %a) { ; SSE-LABEL: test6: ; SSE: # BB#0: ; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psraw $2, %xmm1 -; SSE-NEXT: psraw $3, %xmm0 -; SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; SSE-NEXT: movapd %xmm1, %xmm0 +; SSE-NEXT: psraw $3, %xmm1 +; SSE-NEXT: psraw $2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSE-NEXT: retq ; ; AVX1-LABEL: test6: @@ -170,10 +164,9 @@ define <4 x i32> @test7(<4 x i32> %a) { ; SSE-LABEL: test7: ; SSE: # BB#0: ; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrad $2, %xmm1 -; SSE-NEXT: psrad $3, %xmm0 -; SSE-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] -; SSE-NEXT: movaps %xmm1, %xmm0 +; SSE-NEXT: psrad $3, %xmm1 +; SSE-NEXT: psrad $2, %xmm0 +; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE-NEXT: retq ; ; AVX1-LABEL: test7: @@ -195,10 +188,9 @@ define <4 x i32> @test8(<4 x i32> %a) { ; SSE-LABEL: test8: ; SSE: # BB#0: ; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrad $2, %xmm1 -; SSE-NEXT: psrad $3, %xmm0 -; SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; SSE-NEXT: movapd %xmm1, %xmm0 +; SSE-NEXT: psrad $3, %xmm1 +; SSE-NEXT: psrad $2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSE-NEXT: retq ; ; AVX1-LABEL: test8: diff --git a/llvm/test/CodeGen/X86/psubus.ll b/llvm/test/CodeGen/X86/psubus.ll index 034bbcd6bf4..2c925e52476 100644 --- a/llvm/test/CodeGen/X86/psubus.ll +++ b/llvm/test/CodeGen/X86/psubus.ll @@ -653,48 +653,47 @@ define <16 x i8> @test14(<16 x i8> %x, <16 x i32> %y) nounwind { ; ; SSSE3-LABEL: test14: ; SSSE3: # BB#0: # %vector.ph -; SSSE3-NEXT: pxor %xmm7, %xmm7 -; SSSE3-NEXT: movdqa %xmm0, %xmm11 -; SSSE3-NEXT: punpcklbw {{.*#+}} xmm11 = xmm11[0],xmm7[0],xmm11[1],xmm7[1],xmm11[2],xmm7[2],xmm11[3],xmm7[3],xmm11[4],xmm7[4],xmm11[5],xmm7[5],xmm11[6],xmm7[6],xmm11[7],xmm7[7] -; SSSE3-NEXT: movdqa %xmm11, %xmm8 -; SSSE3-NEXT: punpcklwd {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3] -; SSSE3-NEXT: punpckhwd {{.*#+}} xmm11 = xmm11[4],xmm7[4],xmm11[5],xmm7[5],xmm11[6],xmm7[6],xmm11[7],xmm7[7] -; SSSE3-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm7[8],xmm0[9],xmm7[9],xmm0[10],xmm7[10],xmm0[11],xmm7[11],xmm0[12],xmm7[12],xmm0[13],xmm7[13],xmm0[14],xmm7[14],xmm0[15],xmm7[15] -; SSSE3-NEXT: movdqa %xmm0, %xmm10 -; SSSE3-NEXT: punpcklwd {{.*#+}} xmm10 = xmm10[0],xmm7[0],xmm10[1],xmm7[1],xmm10[2],xmm7[2],xmm10[3],xmm7[3] -; SSSE3-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm7[4],xmm0[5],xmm7[5],xmm0[6],xmm7[6],xmm0[7],xmm7[7] -; SSSE3-NEXT: movdqa {{.*#+}} xmm7 = [2147483648,2147483648,2147483648,2147483648] -; SSSE3-NEXT: movdqa %xmm4, %xmm9 -; SSSE3-NEXT: pxor %xmm7, %xmm9 -; SSSE3-NEXT: psubd %xmm0, %xmm4 -; SSSE3-NEXT: movdqa %xmm0, %xmm6 -; SSSE3-NEXT: pxor %xmm7, %xmm6 -; SSSE3-NEXT: pcmpgtd %xmm9, %xmm6 -; SSSE3-NEXT: movdqa {{.*#+}} xmm9 = <u,u,u,u,0,4,8,12,u,u,u,u,u,u,u,u> -; SSSE3-NEXT: pshufb %xmm9, %xmm6 -; SSSE3-NEXT: movdqa %xmm3, %xmm5 -; SSSE3-NEXT: pxor %xmm7, %xmm5 -; SSSE3-NEXT: psubd %xmm10, %xmm3 -; SSSE3-NEXT: movdqa %xmm10, %xmm0 -; SSSE3-NEXT: pxor %xmm7, %xmm0 -; SSSE3-NEXT: pcmpgtd %xmm5, %xmm0 -; SSSE3-NEXT: pshufb %xmm9, %xmm0 -; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1] -; SSSE3-NEXT: movdqa %xmm2, %xmm5 -; SSSE3-NEXT: pxor %xmm7, %xmm5 -; SSSE3-NEXT: psubd %xmm11, %xmm2 -; SSSE3-NEXT: pxor %xmm7, %xmm11 -; SSSE3-NEXT: pcmpgtd %xmm5, %xmm11 -; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u> -; SSSE3-NEXT: pshufb %xmm5, %xmm11 +; SSSE3-NEXT: movdqa %xmm0, %xmm5 +; SSSE3-NEXT: pxor %xmm0, %xmm0 +; SSSE3-NEXT: movdqa %xmm5, %xmm7 +; SSSE3-NEXT: punpckhbw {{.*#+}} xmm7 = xmm7[8],xmm0[8],xmm7[9],xmm0[9],xmm7[10],xmm0[10],xmm7[11],xmm0[11],xmm7[12],xmm0[12],xmm7[13],xmm0[13],xmm7[14],xmm0[14],xmm7[15],xmm0[15] +; SSSE3-NEXT: movdqa %xmm7, %xmm8 +; SSSE3-NEXT: punpcklwd {{.*#+}} xmm8 = xmm8[0],xmm0[0],xmm8[1],xmm0[1],xmm8[2],xmm0[2],xmm8[3],xmm0[3] +; SSSE3-NEXT: punpckhwd {{.*#+}} xmm7 = xmm7[4],xmm0[4],xmm7[5],xmm0[5],xmm7[6],xmm0[6],xmm7[7],xmm0[7] +; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm0[0],xmm5[1],xmm0[1],xmm5[2],xmm0[2],xmm5[3],xmm0[3],xmm5[4],xmm0[4],xmm5[5],xmm0[5],xmm5[6],xmm0[6],xmm5[7],xmm0[7] +; SSSE3-NEXT: movdqa %xmm5, %xmm10 +; SSSE3-NEXT: punpcklwd {{.*#+}} xmm10 = xmm10[0],xmm0[0],xmm10[1],xmm0[1],xmm10[2],xmm0[2],xmm10[3],xmm0[3] +; SSSE3-NEXT: punpckhwd {{.*#+}} xmm5 = xmm5[4],xmm0[4],xmm5[5],xmm0[5],xmm5[6],xmm0[6],xmm5[7],xmm0[7] +; SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648] +; SSSE3-NEXT: movdqa %xmm2, %xmm9 +; SSSE3-NEXT: pxor %xmm0, %xmm9 +; SSSE3-NEXT: psubd %xmm5, %xmm2 +; SSSE3-NEXT: pxor %xmm0, %xmm5 +; SSSE3-NEXT: pcmpgtd %xmm9, %xmm5 +; SSSE3-NEXT: movdqa {{.*#+}} xmm9 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u> +; SSSE3-NEXT: pshufb %xmm9, %xmm5 ; SSSE3-NEXT: movdqa %xmm1, %xmm6 -; SSSE3-NEXT: pxor %xmm7, %xmm6 -; SSSE3-NEXT: pxor %xmm8, %xmm7 -; SSSE3-NEXT: pcmpgtd %xmm6, %xmm7 +; SSSE3-NEXT: pxor %xmm0, %xmm6 +; SSSE3-NEXT: psubd %xmm10, %xmm1 +; SSSE3-NEXT: pxor %xmm0, %xmm10 +; SSSE3-NEXT: pcmpgtd %xmm6, %xmm10 +; SSSE3-NEXT: pshufb %xmm9, %xmm10 +; SSSE3-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm5[0],xmm10[1],xmm5[1] +; SSSE3-NEXT: movdqa %xmm4, %xmm5 +; SSSE3-NEXT: pxor %xmm0, %xmm5 +; SSSE3-NEXT: psubd %xmm7, %xmm4 +; SSSE3-NEXT: pxor %xmm0, %xmm7 +; SSSE3-NEXT: pcmpgtd %xmm5, %xmm7 +; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = <u,u,u,u,0,4,8,12,u,u,u,u,u,u,u,u> ; SSSE3-NEXT: pshufb %xmm5, %xmm7 -; SSSE3-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],xmm11[1] -; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm7[0],xmm0[1] -; SSSE3-NEXT: psubd %xmm8, %xmm1 +; SSSE3-NEXT: movdqa %xmm3, %xmm6 +; SSSE3-NEXT: pxor %xmm0, %xmm6 +; SSSE3-NEXT: pxor %xmm8, %xmm0 +; SSSE3-NEXT: pcmpgtd %xmm6, %xmm0 +; SSSE3-NEXT: pshufb %xmm5, %xmm0 +; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1] +; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm10[0],xmm0[1] +; SSSE3-NEXT: psubd %xmm8, %xmm3 ; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; SSSE3-NEXT: pand %xmm5, %xmm4 ; SSSE3-NEXT: pand %xmm5, %xmm3 @@ -1668,16 +1667,16 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; SSE2: # BB#0: # %vector.ph ; SSE2-NEXT: pxor %xmm5, %xmm5 ; SSE2-NEXT: movdqa %xmm0, %xmm10 -; SSE2-NEXT: punpckhwd {{.*#+}} xmm10 = xmm10[4],xmm5[4],xmm10[5],xmm5[5],xmm10[6],xmm5[6],xmm10[7],xmm5[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm10 = xmm10[0],xmm5[0],xmm10[1],xmm5[1],xmm10[2],xmm5[2],xmm10[3],xmm5[3] ; SSE2-NEXT: movdqa %xmm10, %xmm9 ; SSE2-NEXT: punpckhdq {{.*#+}} xmm9 = xmm9[2],xmm5[2],xmm9[3],xmm5[3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm5[0],xmm10[1],xmm5[1] -; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3] +; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm5[4],xmm0[5],xmm5[5],xmm0[6],xmm5[6],xmm0[7],xmm5[7] ; SSE2-NEXT: movdqa %xmm0, %xmm8 ; SSE2-NEXT: punpckhdq {{.*#+}} xmm8 = xmm8[2],xmm5[2],xmm8[3],xmm5[3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1] ; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [2147483648,2147483648,2147483648,2147483648] -; SSE2-NEXT: movdqa %xmm1, %xmm5 +; SSE2-NEXT: movdqa %xmm3, %xmm5 ; SSE2-NEXT: pxor %xmm6, %xmm5 ; SSE2-NEXT: movdqa %xmm0, %xmm7 ; SSE2-NEXT: por %xmm6, %xmm7 @@ -1689,7 +1688,7 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; SSE2-NEXT: pand %xmm12, %xmm5 ; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm11[1,1,3,3] ; SSE2-NEXT: por %xmm5, %xmm11 -; SSE2-NEXT: movdqa %xmm2, %xmm5 +; SSE2-NEXT: movdqa %xmm4, %xmm5 ; SSE2-NEXT: pxor %xmm6, %xmm5 ; SSE2-NEXT: movdqa %xmm8, %xmm7 ; SSE2-NEXT: por %xmm6, %xmm7 @@ -1701,7 +1700,7 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; SSE2-NEXT: pand %xmm13, %xmm5 ; SSE2-NEXT: pshufd {{.*#+}} xmm12 = xmm12[1,1,3,3] ; SSE2-NEXT: por %xmm5, %xmm12 -; SSE2-NEXT: movdqa %xmm3, %xmm5 +; SSE2-NEXT: movdqa %xmm1, %xmm5 ; SSE2-NEXT: pxor %xmm6, %xmm5 ; SSE2-NEXT: movdqa %xmm10, %xmm7 ; SSE2-NEXT: por %xmm6, %xmm7 @@ -1713,7 +1712,7 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; SSE2-NEXT: pand %xmm14, %xmm7 ; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm13[1,1,3,3] ; SSE2-NEXT: por %xmm7, %xmm13 -; SSE2-NEXT: movdqa %xmm4, %xmm7 +; SSE2-NEXT: movdqa %xmm2, %xmm7 ; SSE2-NEXT: pxor %xmm6, %xmm7 ; SSE2-NEXT: por %xmm9, %xmm6 ; SSE2-NEXT: movdqa %xmm7, %xmm5 @@ -1724,53 +1723,53 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; SSE2-NEXT: pand %xmm14, %xmm7 ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3] ; SSE2-NEXT: por %xmm7, %xmm6 -; SSE2-NEXT: movdqa %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm2, %xmm5 ; SSE2-NEXT: pand %xmm6, %xmm5 ; SSE2-NEXT: pandn %xmm9, %xmm6 ; SSE2-NEXT: por %xmm5, %xmm6 -; SSE2-NEXT: movdqa %xmm3, %xmm5 +; SSE2-NEXT: movdqa %xmm1, %xmm5 ; SSE2-NEXT: pand %xmm13, %xmm5 ; SSE2-NEXT: pandn %xmm10, %xmm13 ; SSE2-NEXT: por %xmm5, %xmm13 -; SSE2-NEXT: movdqa %xmm2, %xmm5 +; SSE2-NEXT: movdqa %xmm4, %xmm5 ; SSE2-NEXT: pand %xmm12, %xmm5 ; SSE2-NEXT: pandn %xmm8, %xmm12 ; SSE2-NEXT: por %xmm5, %xmm12 -; SSE2-NEXT: movdqa %xmm1, %xmm5 +; SSE2-NEXT: movdqa %xmm3, %xmm5 ; SSE2-NEXT: pand %xmm11, %xmm5 ; SSE2-NEXT: pandn %xmm0, %xmm11 ; SSE2-NEXT: por %xmm5, %xmm11 -; SSE2-NEXT: psubq %xmm1, %xmm11 -; SSE2-NEXT: psubq %xmm2, %xmm12 -; SSE2-NEXT: psubq %xmm3, %xmm13 -; SSE2-NEXT: psubq %xmm4, %xmm6 +; SSE2-NEXT: psubq %xmm3, %xmm11 +; SSE2-NEXT: psubq %xmm4, %xmm12 +; SSE2-NEXT: psubq %xmm1, %xmm13 +; SSE2-NEXT: psubq %xmm2, %xmm6 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm13[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] -; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm12[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm13[0,2,2,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm11[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] -; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] -; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm12[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,1,0,2,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm11[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSE2-NEXT: retq ; ; SSSE3-LABEL: psubus_8i64_max: ; SSSE3: # BB#0: # %vector.ph ; SSSE3-NEXT: pxor %xmm5, %xmm5 ; SSSE3-NEXT: movdqa %xmm0, %xmm10 -; SSSE3-NEXT: punpckhwd {{.*#+}} xmm10 = xmm10[4],xmm5[4],xmm10[5],xmm5[5],xmm10[6],xmm5[6],xmm10[7],xmm5[7] +; SSSE3-NEXT: punpcklwd {{.*#+}} xmm10 = xmm10[0],xmm5[0],xmm10[1],xmm5[1],xmm10[2],xmm5[2],xmm10[3],xmm5[3] ; SSSE3-NEXT: movdqa %xmm10, %xmm9 ; SSSE3-NEXT: punpckhdq {{.*#+}} xmm9 = xmm9[2],xmm5[2],xmm9[3],xmm5[3] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm5[0],xmm10[1],xmm5[1] -; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3] +; SSSE3-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm5[4],xmm0[5],xmm5[5],xmm0[6],xmm5[6],xmm0[7],xmm5[7] ; SSSE3-NEXT: movdqa %xmm0, %xmm8 ; SSSE3-NEXT: punpckhdq {{.*#+}} xmm8 = xmm8[2],xmm5[2],xmm8[3],xmm5[3] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1] ; SSSE3-NEXT: movdqa {{.*#+}} xmm6 = [2147483648,2147483648,2147483648,2147483648] -; SSSE3-NEXT: movdqa %xmm1, %xmm5 +; SSSE3-NEXT: movdqa %xmm3, %xmm5 ; SSSE3-NEXT: pxor %xmm6, %xmm5 ; SSSE3-NEXT: movdqa %xmm0, %xmm7 ; SSSE3-NEXT: por %xmm6, %xmm7 @@ -1782,7 +1781,7 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; SSSE3-NEXT: pand %xmm12, %xmm5 ; SSSE3-NEXT: pshufd {{.*#+}} xmm11 = xmm11[1,1,3,3] ; SSSE3-NEXT: por %xmm5, %xmm11 -; SSSE3-NEXT: movdqa %xmm2, %xmm5 +; SSSE3-NEXT: movdqa %xmm4, %xmm5 ; SSSE3-NEXT: pxor %xmm6, %xmm5 ; SSSE3-NEXT: movdqa %xmm8, %xmm7 ; SSSE3-NEXT: por %xmm6, %xmm7 @@ -1794,7 +1793,7 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; SSSE3-NEXT: pand %xmm13, %xmm5 ; SSSE3-NEXT: pshufd {{.*#+}} xmm12 = xmm12[1,1,3,3] ; SSSE3-NEXT: por %xmm5, %xmm12 -; SSSE3-NEXT: movdqa %xmm3, %xmm5 +; SSSE3-NEXT: movdqa %xmm1, %xmm5 ; SSSE3-NEXT: pxor %xmm6, %xmm5 ; SSSE3-NEXT: movdqa %xmm10, %xmm7 ; SSSE3-NEXT: por %xmm6, %xmm7 @@ -1806,7 +1805,7 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; SSSE3-NEXT: pand %xmm14, %xmm7 ; SSSE3-NEXT: pshufd {{.*#+}} xmm13 = xmm13[1,1,3,3] ; SSSE3-NEXT: por %xmm7, %xmm13 -; SSSE3-NEXT: movdqa %xmm4, %xmm7 +; SSSE3-NEXT: movdqa %xmm2, %xmm7 ; SSSE3-NEXT: pxor %xmm6, %xmm7 ; SSSE3-NEXT: por %xmm9, %xmm6 ; SSSE3-NEXT: movdqa %xmm7, %xmm5 @@ -1817,37 +1816,37 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; SSSE3-NEXT: pand %xmm14, %xmm7 ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3] ; SSSE3-NEXT: por %xmm7, %xmm6 -; SSSE3-NEXT: movdqa %xmm4, %xmm5 +; SSSE3-NEXT: movdqa %xmm2, %xmm5 ; SSSE3-NEXT: pand %xmm6, %xmm5 ; SSSE3-NEXT: pandn %xmm9, %xmm6 ; SSSE3-NEXT: por %xmm5, %xmm6 -; SSSE3-NEXT: movdqa %xmm3, %xmm5 +; SSSE3-NEXT: movdqa %xmm1, %xmm5 ; SSSE3-NEXT: pand %xmm13, %xmm5 ; SSSE3-NEXT: pandn %xmm10, %xmm13 ; SSSE3-NEXT: por %xmm5, %xmm13 -; SSSE3-NEXT: movdqa %xmm2, %xmm5 +; SSSE3-NEXT: movdqa %xmm4, %xmm5 ; SSSE3-NEXT: pand %xmm12, %xmm5 ; SSSE3-NEXT: pandn %xmm8, %xmm12 ; SSSE3-NEXT: por %xmm5, %xmm12 -; SSSE3-NEXT: movdqa %xmm1, %xmm5 +; SSSE3-NEXT: movdqa %xmm3, %xmm5 ; SSSE3-NEXT: pand %xmm11, %xmm5 ; SSSE3-NEXT: pandn %xmm0, %xmm11 ; SSSE3-NEXT: por %xmm5, %xmm11 -; SSSE3-NEXT: psubq %xmm1, %xmm11 -; SSSE3-NEXT: psubq %xmm2, %xmm12 -; SSSE3-NEXT: psubq %xmm3, %xmm13 -; SSSE3-NEXT: psubq %xmm4, %xmm6 +; SSSE3-NEXT: psubq %xmm3, %xmm11 +; SSSE3-NEXT: psubq %xmm4, %xmm12 +; SSSE3-NEXT: psubq %xmm1, %xmm13 +; SSSE3-NEXT: psubq %xmm2, %xmm6 ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,2,2,3] -; SSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] -; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm13[0,2,2,3] -; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] -; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm12[0,2,2,3] +; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm13[0,2,2,3] ; SSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] -; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm11[0,2,2,3] -; SSSE3-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] -; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] -; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm12[0,2,2,3] +; SSSE3-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,1,0,2,4,5,6,7] +; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm11[0,2,2,3] +; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] +; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSSE3-NEXT: retq ; ; SSE41-LABEL: psubus_8i64_max: diff --git a/llvm/test/CodeGen/X86/vector-blend.ll b/llvm/test/CodeGen/X86/vector-blend.ll index 03aebed9274..831d2a7970b 100644 --- a/llvm/test/CodeGen/X86/vector-blend.ll +++ b/llvm/test/CodeGen/X86/vector-blend.ll @@ -724,8 +724,8 @@ define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b) ; ; SSE41-LABEL: blend_shufflevector_8xfloat: ; SSE41: # BB#0: # %entry -; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm3[0,1],xmm1[2],xmm3[3] ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3] +; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm3[0,1],xmm1[2],xmm3[3] ; SSE41-NEXT: retq ; ; AVX-LABEL: blend_shufflevector_8xfloat: diff --git a/llvm/test/CodeGen/X86/vector-compare-results.ll b/llvm/test/CodeGen/X86/vector-compare-results.ll index 473d54d28a6..a9d3152fd6b 100644 --- a/llvm/test/CodeGen/X86/vector-compare-results.ll +++ b/llvm/test/CodeGen/X86/vector-compare-results.ll @@ -7895,89 +7895,89 @@ define <32 x i1> @test_cmp_v32f64(<32 x double> %a0, <32 x double> %a1) nounwind ; SSE2-LABEL: test_cmp_v32f64: ; SSE2: # BB#0: ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm8 -; SSE2-NEXT: cmpltpd %xmm7, %xmm8 -; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm7 -; SSE2-NEXT: cmpltpd %xmm6, %xmm7 -; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm8 = xmm8[0,1,0,2,4,5,6,7] -; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm7[0,1,0,2,4,5,6,7] -; SSE2-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm8[0],xmm6[1],xmm8[1] -; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm7 -; SSE2-NEXT: cmpltpd %xmm5, %xmm7 +; SSE2-NEXT: cmpltpd %xmm5, %xmm8 ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm5 ; SSE2-NEXT: cmpltpd %xmm4, %xmm5 -; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm7[0,2,2,3,4,5,6,7] +; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm8[0,2,2,3,4,5,6,7] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2,2,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7] ; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] -; SSE2-NEXT: movsd {{.*#+}} xmm6 = xmm5[0],xmm6[1] ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm4 -; SSE2-NEXT: cmpltpd %xmm3, %xmm4 -; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm5 -; SSE2-NEXT: cmpltpd %xmm2, %xmm5 -; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm3 +; SSE2-NEXT: cmpltpd %xmm7, %xmm4 +; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm7 +; SSE2-NEXT: cmpltpd %xmm6, %xmm7 ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,1,0,2,4,5,6,7] -; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm5[0,1,0,2,4,5,6,7] -; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1] -; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm4 -; SSE2-NEXT: cmpltpd %xmm1, %xmm4 -; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm1 -; SSE2-NEXT: cmpltpd %xmm0, %xmm1 +; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm4[0,1,0,2,4,5,6,7] +; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm7[0,1,0,2,4,5,6,7] +; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1] +; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm5[0],xmm4[1] ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm5 -; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm4[0,2,2,3,4,5,6,7] -; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] -; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] -; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm4 -; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1] -; SSE2-NEXT: movapd {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255] -; SSE2-NEXT: andpd %xmm0, %xmm6 -; SSE2-NEXT: andpd %xmm0, %xmm2 -; SSE2-NEXT: packuswb %xmm6, %xmm2 +; SSE2-NEXT: cmpltpd %xmm1, %xmm5 +; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm6 +; SSE2-NEXT: cmpltpd %xmm0, %xmm6 ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm1 -; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm1 -; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm1[0,1,0,2,4,5,6,7] -; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm4 -; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm4[0,1,0,2,4,5,6,7] -; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1] +; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm5[0,2,2,3,4,5,6,7] +; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm6[0,2,2,3,4,5,6,7] +; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm0[0],xmm5[1],xmm0[1] +; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm0 +; SSE2-NEXT: cmpltpd %xmm3, %xmm0 +; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm3 +; SSE2-NEXT: cmpltpd %xmm2, %xmm3 +; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm6 +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,1,0,2,4,5,6,7] +; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm3[0,1,0,2,4,5,6,7] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm3 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm5[0],xmm0[1] +; SSE2-NEXT: movapd {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] +; SSE2-NEXT: andpd %xmm2, %xmm4 +; SSE2-NEXT: andpd %xmm2, %xmm0 +; SSE2-NEXT: packuswb %xmm4, %xmm0 ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm4 ; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm4 ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2,2,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7] -; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm5 -; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7] +; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm3 +; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm3[0,2,2,3,4,5,6,7] ; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] +; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm3 +; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm3 +; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm3[0,1,0,2,4,5,6,7] +; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm6 +; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm6[0,1,0,2,4,5,6,7] +; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1] ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm4 -; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm5[0],xmm1[1] +; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm5[0],xmm3[1] ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm5 ; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm5 ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,1,0,2,4,5,6,7] +; SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7] ; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm4 ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,1,0,2,4,5,6,7] +; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7] ; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE2-NEXT: movapd {{[0-9]+}}(%rsp), %xmm5 ; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm5 ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7] -; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm3 -; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7] -; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1] -; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1] -; SSE2-NEXT: andpd %xmm0, %xmm1 -; SSE2-NEXT: andpd %xmm0, %xmm4 -; SSE2-NEXT: packuswb %xmm1, %xmm4 -; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,1,0,2,4,5,6,7] +; SSE2-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm1 +; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,0,2,4,5,6,7] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1] +; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm4[0],xmm1[1] +; SSE2-NEXT: andpd %xmm2, %xmm3 +; SSE2-NEXT: andpd %xmm2, %xmm1 +; SSE2-NEXT: packuswb %xmm3, %xmm1 +; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp) ; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al ; SSE2-NEXT: andb $1, %al ; SSE2-NEXT: movb %al, 2(%rdi) @@ -8026,7 +8026,7 @@ define <32 x i1> @test_cmp_v32f64(<32 x double> %a0, <32 x double> %a1) nounwind ; SSE2-NEXT: movb %cl, 2(%rdi) ; SSE2-NEXT: andb $1, %al ; SSE2-NEXT: movb %al, 2(%rdi) -; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) ; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al ; SSE2-NEXT: andb $1, %al ; SSE2-NEXT: movb %al, (%rdi) @@ -9010,26 +9010,57 @@ define <32 x i1> @test_cmp_v32i64(<32 x i64> %a0, <32 x i64> %a1) nounwind { ; SSE2-NEXT: pcmpgtd %xmm9, %xmm11 ; SSE2-NEXT: pshufd {{.*#+}} xmm12 = xmm11[0,0,2,2] ; SSE2-NEXT: pcmpeqd %xmm9, %xmm10 -; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm10[1,1,3,3] -; SSE2-NEXT: pand %xmm12, %xmm9 -; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm11[1,1,3,3] -; SSE2-NEXT: por %xmm9, %xmm10 -; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 -; SSE2-NEXT: pxor %xmm8, %xmm9 +; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm10[1,1,3,3] +; SSE2-NEXT: pand %xmm12, %xmm10 +; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm11[1,1,3,3] +; SSE2-NEXT: por %xmm10, %xmm9 +; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10 +; SSE2-NEXT: pxor %xmm8, %xmm10 ; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11 ; SSE2-NEXT: pxor %xmm8, %xmm11 ; SSE2-NEXT: movdqa %xmm11, %xmm12 -; SSE2-NEXT: pcmpgtd %xmm9, %xmm12 +; SSE2-NEXT: pcmpgtd %xmm10, %xmm12 ; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm12[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm9, %xmm11 -; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm11[1,1,3,3] -; SSE2-NEXT: pand %xmm13, %xmm9 +; SSE2-NEXT: pcmpeqd %xmm10, %xmm11 +; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm11[1,1,3,3] +; SSE2-NEXT: pand %xmm13, %xmm11 +; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm12[1,1,3,3] +; SSE2-NEXT: por %xmm11, %xmm10 +; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm10[2,3,0,1] +; SSE2-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,2],xmm9[0,2] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm10 = xmm10[0],xmm11[0],xmm10[1],xmm11[1],xmm10[2],xmm11[2],xmm10[3],xmm11[3] +; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11 +; SSE2-NEXT: pxor %xmm8, %xmm11 +; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12 +; SSE2-NEXT: pxor %xmm8, %xmm12 +; SSE2-NEXT: movdqa %xmm12, %xmm13 +; SSE2-NEXT: pcmpgtd %xmm11, %xmm13 +; SSE2-NEXT: pshufd {{.*#+}} xmm14 = xmm13[0,0,2,2] +; SSE2-NEXT: pcmpeqd %xmm11, %xmm12 ; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm12[1,1,3,3] -; SSE2-NEXT: por %xmm9, %xmm11 -; SSE2-NEXT: shufps {{.*#+}} xmm11 = xmm11[0,2],xmm10[0,2] -; SSE2-NEXT: pshuflw {{.*#+}} xmm9 = xmm11[0,2,2,3,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm9 = xmm9[0,1,2,3,4,6,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm9[0,1,0,2] +; SSE2-NEXT: pand %xmm14, %xmm11 +; SSE2-NEXT: pshufd {{.*#+}} xmm12 = xmm13[1,1,3,3] +; SSE2-NEXT: por %xmm11, %xmm12 +; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11 +; SSE2-NEXT: pxor %xmm8, %xmm11 +; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13 +; SSE2-NEXT: pxor %xmm8, %xmm13 +; SSE2-NEXT: movdqa %xmm13, %xmm14 +; SSE2-NEXT: pcmpgtd %xmm11, %xmm14 +; SSE2-NEXT: pshufd {{.*#+}} xmm15 = xmm14[0,0,2,2] +; SSE2-NEXT: pcmpeqd %xmm11, %xmm13 +; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm13[1,1,3,3] +; SSE2-NEXT: pand %xmm15, %xmm11 +; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm14[1,1,3,3] +; SSE2-NEXT: por %xmm11, %xmm13 +; SSE2-NEXT: shufps {{.*#+}} xmm13 = xmm13[0,2],xmm12[0,2] +; SSE2-NEXT: pshuflw {{.*#+}} xmm11 = xmm13[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm11 = xmm11[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm11[0,1,0,2] +; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm9[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm9 = xmm9[0,1,0,2,4,5,6,7] +; SSE2-NEXT: movsd {{.*#+}} xmm11 = xmm9[0],xmm11[1] +; SSE2-NEXT: movss {{.*#+}} xmm11 = xmm10[0],xmm11[1,2,3] ; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE2-NEXT: pxor %xmm8, %xmm9 ; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10 @@ -9042,9 +9073,6 @@ define <32 x i1> @test_cmp_v32i64(<32 x i64> %a0, <32 x i64> %a1) nounwind { ; SSE2-NEXT: pand %xmm13, %xmm9 ; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm12[1,1,3,3] ; SSE2-NEXT: por %xmm9, %xmm10 -; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm10[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm9 = xmm9[0,1,0,2,4,5,6,7] -; SSE2-NEXT: movsd {{.*#+}} xmm11 = xmm9[0],xmm11[1] ; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE2-NEXT: pxor %xmm8, %xmm9 ; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12 @@ -9060,68 +9088,40 @@ define <32 x i1> @test_cmp_v32i64(<32 x i64> %a0, <32 x i64> %a1) nounwind { ; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm12[2,3,0,1] ; SSE2-NEXT: shufps {{.*#+}} xmm12 = xmm12[0,2],xmm10[0,2] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm12 = xmm12[0],xmm9[0],xmm12[1],xmm9[1],xmm12[2],xmm9[2],xmm12[3],xmm9[3] -; SSE2-NEXT: movss {{.*#+}} xmm11 = xmm12[0],xmm11[1,2,3] ; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE2-NEXT: pxor %xmm8, %xmm9 -; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10 -; SSE2-NEXT: pxor %xmm8, %xmm10 -; SSE2-NEXT: movdqa %xmm10, %xmm12 -; SSE2-NEXT: pcmpgtd %xmm9, %xmm12 -; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm12[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm9, %xmm10 -; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm10[1,1,3,3] -; SSE2-NEXT: pand %xmm13, %xmm9 -; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm12[1,1,3,3] -; SSE2-NEXT: por %xmm9, %xmm10 +; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13 +; SSE2-NEXT: pxor %xmm8, %xmm13 +; SSE2-NEXT: movdqa %xmm13, %xmm14 +; SSE2-NEXT: pcmpgtd %xmm9, %xmm14 +; SSE2-NEXT: pshufd {{.*#+}} xmm15 = xmm14[0,0,2,2] +; SSE2-NEXT: pcmpeqd %xmm9, %xmm13 +; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm13[1,1,3,3] +; SSE2-NEXT: pand %xmm15, %xmm9 +; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm14[1,1,3,3] +; SSE2-NEXT: por %xmm9, %xmm13 ; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE2-NEXT: pxor %xmm8, %xmm9 -; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12 -; SSE2-NEXT: pxor %xmm8, %xmm12 -; SSE2-NEXT: movdqa %xmm12, %xmm13 -; SSE2-NEXT: pcmpgtd %xmm9, %xmm13 -; SSE2-NEXT: pshufd {{.*#+}} xmm14 = xmm13[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm9, %xmm12 -; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm12[1,1,3,3] -; SSE2-NEXT: pand %xmm14, %xmm9 -; SSE2-NEXT: pshufd {{.*#+}} xmm12 = xmm13[1,1,3,3] -; SSE2-NEXT: por %xmm9, %xmm12 -; SSE2-NEXT: shufps {{.*#+}} xmm12 = xmm12[0,2],xmm10[0,2] -; SSE2-NEXT: pshuflw {{.*#+}} xmm9 = xmm12[0,2,2,3,4,5,6,7] +; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14 +; SSE2-NEXT: pxor %xmm8, %xmm14 +; SSE2-NEXT: movdqa %xmm14, %xmm15 +; SSE2-NEXT: pcmpgtd %xmm9, %xmm15 +; SSE2-NEXT: pcmpeqd %xmm9, %xmm14 +; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm15[0,0,2,2] +; SSE2-NEXT: pshufd {{.*#+}} xmm14 = xmm14[1,1,3,3] +; SSE2-NEXT: pand %xmm9, %xmm14 +; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm15[1,1,3,3] +; SSE2-NEXT: por %xmm14, %xmm9 +; SSE2-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,2],xmm13[0,2] +; SSE2-NEXT: pshuflw {{.*#+}} xmm9 = xmm9[0,2,2,3,4,5,6,7] ; SSE2-NEXT: pshufhw {{.*#+}} xmm9 = xmm9[0,1,2,3,4,6,6,7] ; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm9[0,1,0,2] -; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10 -; SSE2-NEXT: pxor %xmm8, %xmm10 -; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12 -; SSE2-NEXT: pxor %xmm8, %xmm12 -; SSE2-NEXT: movdqa %xmm12, %xmm13 -; SSE2-NEXT: pcmpgtd %xmm10, %xmm13 -; SSE2-NEXT: pshufd {{.*#+}} xmm14 = xmm13[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm10, %xmm12 -; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm12[1,1,3,3] -; SSE2-NEXT: pand %xmm14, %xmm10 -; SSE2-NEXT: pshufd {{.*#+}} xmm12 = xmm13[1,1,3,3] -; SSE2-NEXT: por %xmm10, %xmm12 -; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm12[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm10[0,2,2,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm10 = xmm10[0,1,0,2,4,5,6,7] ; SSE2-NEXT: movsd {{.*#+}} xmm9 = xmm10[0],xmm9[1] -; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10 -; SSE2-NEXT: pxor %xmm8, %xmm10 -; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13 -; SSE2-NEXT: pxor %xmm8, %xmm13 -; SSE2-NEXT: movdqa %xmm13, %xmm14 -; SSE2-NEXT: pcmpgtd %xmm10, %xmm14 -; SSE2-NEXT: pcmpeqd %xmm10, %xmm13 -; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm14[0,0,2,2] -; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm13[1,1,3,3] -; SSE2-NEXT: pand %xmm10, %xmm13 -; SSE2-NEXT: pshufd {{.*#+}} xmm14 = xmm14[1,1,3,3] -; SSE2-NEXT: por %xmm13, %xmm14 -; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm14[2,3,0,1] -; SSE2-NEXT: shufps {{.*#+}} xmm14 = xmm14[0,2],xmm12[0,2] -; SSE2-NEXT: punpcklwd {{.*#+}} xmm14 = xmm14[0],xmm10[0],xmm14[1],xmm10[1],xmm14[2],xmm10[2],xmm14[3],xmm10[3] ; SSE2-NEXT: movaps {{.*#+}} xmm10 = [255,255,255,255,255,255,255,255] ; SSE2-NEXT: andps %xmm10, %xmm11 -; SSE2-NEXT: movss {{.*#+}} xmm9 = xmm14[0],xmm9[1,2,3] +; SSE2-NEXT: movss {{.*#+}} xmm9 = xmm12[0],xmm9[1,2,3] ; SSE2-NEXT: andps %xmm10, %xmm9 ; SSE2-NEXT: packuswb %xmm11, %xmm9 ; SSE2-NEXT: pxor %xmm8, %xmm5 diff --git a/llvm/test/CodeGen/X86/vector-rotate-128.ll b/llvm/test/CodeGen/X86/vector-rotate-128.ll index 2d407290acc..afcc053bb6a 100644 --- a/llvm/test/CodeGen/X86/vector-rotate-128.ll +++ b/llvm/test/CodeGen/X86/vector-rotate-128.ll @@ -20,19 +20,18 @@ define <2 x i64> @var_rotate_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; SSE2: # BB#0: ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [64,64] ; SSE2-NEXT: psubq %xmm1, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] -; SSE2-NEXT: movdqa %xmm0, %xmm4 -; SSE2-NEXT: psllq %xmm3, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: psllq %xmm1, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; SSE2-NEXT: movdqa %xmm0, %xmm4 +; SSE2-NEXT: psllq %xmm1, %xmm4 ; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,0,1] ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psrlq %xmm3, %xmm1 +; SSE2-NEXT: psrlq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] ; SSE2-NEXT: psrlq %xmm2, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; SSE2-NEXT: orpd %xmm4, %xmm1 -; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: orpd %xmm4, %xmm0 ; SSE2-NEXT: retq ; ; SSE41-LABEL: var_rotate_v2i64: @@ -100,19 +99,18 @@ define <2 x i64> @var_rotate_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [64,0,64,0] ; X32-SSE-NEXT: psubq %xmm1, %xmm2 -; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] -; X32-SSE-NEXT: movdqa %xmm0, %xmm4 -; X32-SSE-NEXT: psllq %xmm3, %xmm4 ; X32-SSE-NEXT: movdqa %xmm0, %xmm3 ; X32-SSE-NEXT: psllq %xmm1, %xmm3 +; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; X32-SSE-NEXT: movdqa %xmm0, %xmm4 +; X32-SSE-NEXT: psllq %xmm1, %xmm4 ; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,0,1] ; X32-SSE-NEXT: movdqa %xmm0, %xmm1 -; X32-SSE-NEXT: psrlq %xmm3, %xmm1 +; X32-SSE-NEXT: psrlq %xmm2, %xmm1 +; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] ; X32-SSE-NEXT: psrlq %xmm2, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; X32-SSE-NEXT: orpd %xmm4, %xmm1 -; X32-SSE-NEXT: movapd %xmm1, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; X32-SSE-NEXT: orpd %xmm4, %xmm0 ; X32-SSE-NEXT: retl %b64 = sub <2 x i64> <i64 64, i64 64>, %b %shl = shl <2 x i64> %a, %b @@ -137,24 +135,24 @@ define <4 x i32> @var_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] ; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: psrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; SSE2-NEXT: psrlq $32, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm4 ; SSE2-NEXT: psrld %xmm3, %xmm4 ; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: psrlq $32, %xmm3 +; SSE2-NEXT: psrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: psrld %xmm3, %xmm5 -; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm5[0],xmm4[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,3,2,3] +; SSE2-NEXT: movsd {{.*#+}} xmm5 = xmm4[0],xmm5[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm5[1,3,2,3] ; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: movdqa %xmm2, %xmm5 -; SSE2-NEXT: punpckhdq {{.*#+}} xmm5 = xmm5[2],xmm4[2],xmm5[3],xmm4[3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; SSE2-NEXT: movdqa %xmm0, %xmm6 ; SSE2-NEXT: psrld %xmm5, %xmm6 -; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1] +; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm4[2],xmm2[3],xmm4[3] ; SSE2-NEXT: psrld %xmm2, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm6 = xmm0[0],xmm6[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,2,2,3] +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm6[0],xmm0[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: retq @@ -253,24 +251,24 @@ define <4 x i32> @var_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { ; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3] ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] ; X32-SSE-NEXT: movdqa %xmm2, %xmm3 -; X32-SSE-NEXT: psrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; X32-SSE-NEXT: psrlq $32, %xmm3 ; X32-SSE-NEXT: movdqa %xmm0, %xmm4 ; X32-SSE-NEXT: psrld %xmm3, %xmm4 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3 -; X32-SSE-NEXT: psrlq $32, %xmm3 +; X32-SSE-NEXT: psrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X32-SSE-NEXT: movdqa %xmm0, %xmm5 ; X32-SSE-NEXT: psrld %xmm3, %xmm5 -; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm5[0],xmm4[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,3,2,3] +; X32-SSE-NEXT: movsd {{.*#+}} xmm5 = xmm4[0],xmm5[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm5[1,3,2,3] ; X32-SSE-NEXT: pxor %xmm4, %xmm4 ; X32-SSE-NEXT: movdqa %xmm2, %xmm5 -; X32-SSE-NEXT: punpckhdq {{.*#+}} xmm5 = xmm5[2],xmm4[2],xmm5[3],xmm4[3] +; X32-SSE-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; X32-SSE-NEXT: movdqa %xmm0, %xmm6 ; X32-SSE-NEXT: psrld %xmm5, %xmm6 -; X32-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1] +; X32-SSE-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm4[2],xmm2[3],xmm4[3] ; X32-SSE-NEXT: psrld %xmm2, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm6 = xmm0[0],xmm6[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,2,2,3] +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm6[0],xmm0[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] ; X32-SSE-NEXT: por %xmm1, %xmm0 ; X32-SSE-NEXT: retl @@ -794,17 +792,16 @@ define <16 x i8> @var_rotate_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind { define <2 x i64> @constant_rotate_v2i64(<2 x i64> %a) nounwind { ; SSE2-LABEL: constant_rotate_v2i64: ; SSE2: # BB#0: -; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: psllq $14, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: psllq $4, %xmm1 +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: psllq $14, %xmm2 ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1] ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psrlq $50, %xmm1 -; SSE2-NEXT: psrlq $60, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; SSE2-NEXT: orpd %xmm2, %xmm1 -; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: psrlq $60, %xmm1 +; SSE2-NEXT: psrlq $50, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: orpd %xmm2, %xmm0 ; SSE2-NEXT: retq ; ; SSE41-LABEL: constant_rotate_v2i64: @@ -860,17 +857,16 @@ define <2 x i64> @constant_rotate_v2i64(<2 x i64> %a) nounwind { ; ; X32-SSE-LABEL: constant_rotate_v2i64: ; X32-SSE: # BB#0: -; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: psllq $14, %xmm2 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1 ; X32-SSE-NEXT: psllq $4, %xmm1 +; X32-SSE-NEXT: movdqa %xmm0, %xmm2 +; X32-SSE-NEXT: psllq $14, %xmm2 ; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1] ; X32-SSE-NEXT: movdqa %xmm0, %xmm1 -; X32-SSE-NEXT: psrlq $50, %xmm1 -; X32-SSE-NEXT: psrlq $60, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; X32-SSE-NEXT: orpd %xmm2, %xmm1 -; X32-SSE-NEXT: movapd %xmm1, %xmm0 +; X32-SSE-NEXT: psrlq $60, %xmm1 +; X32-SSE-NEXT: psrlq $50, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; X32-SSE-NEXT: orpd %xmm2, %xmm0 ; X32-SSE-NEXT: retl %shl = shl <2 x i64> %a, <i64 4, i64 14> %lshr = lshr <2 x i64> %a, <i64 60, i64 50> @@ -891,16 +887,16 @@ define <4 x i32> @constant_rotate_v4i32(<4 x i32> %a) nounwind { ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psrld $25, %xmm1 +; SSE2-NEXT: psrld $27, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm3 -; SSE2-NEXT: psrld $27, %xmm3 -; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm3[0],xmm1[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] +; SSE2-NEXT: psrld $25, %xmm3 +; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] ; SSE2-NEXT: movdqa %xmm0, %xmm3 -; SSE2-NEXT: psrld $26, %xmm3 -; SSE2-NEXT: psrld $28, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE2-NEXT: psrld $28, %xmm3 +; SSE2-NEXT: psrld $26, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm3[0],xmm0[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: retq @@ -973,16 +969,16 @@ define <4 x i32> @constant_rotate_v4i32(<4 x i32> %a) nounwind { ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3] ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; X32-SSE-NEXT: movdqa %xmm0, %xmm1 -; X32-SSE-NEXT: psrld $25, %xmm1 +; X32-SSE-NEXT: psrld $27, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm3 -; X32-SSE-NEXT: psrld $27, %xmm3 -; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm3[0],xmm1[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] +; X32-SSE-NEXT: psrld $25, %xmm3 +; X32-SSE-NEXT: movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] ; X32-SSE-NEXT: movdqa %xmm0, %xmm3 -; X32-SSE-NEXT: psrld $26, %xmm3 -; X32-SSE-NEXT: psrld $28, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; X32-SSE-NEXT: psrld $28, %xmm3 +; X32-SSE-NEXT: psrld $26, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm3[0],xmm0[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X32-SSE-NEXT: por %xmm2, %xmm0 ; X32-SSE-NEXT: retl diff --git a/llvm/test/CodeGen/X86/vector-shift-ashr-128.ll b/llvm/test/CodeGen/X86/vector-shift-ashr-128.ll index 8e981f45864..55766daecff 100644 --- a/llvm/test/CodeGen/X86/vector-shift-ashr-128.ll +++ b/llvm/test/CodeGen/X86/vector-shift-ashr-128.ll @@ -20,19 +20,18 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; SSE2-LABEL: var_shift_v2i64: ; SSE2: # BB#0: -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] -; SSE2-NEXT: movdqa %xmm2, %xmm4 -; SSE2-NEXT: psrlq %xmm3, %xmm4 -; SSE2-NEXT: psrlq %xmm1, %xmm2 -; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm2[0],xmm4[1] -; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: psrlq %xmm3, %xmm2 -; SSE2-NEXT: psrlq %xmm1, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE2-NEXT: xorpd %xmm4, %xmm2 -; SSE2-NEXT: psubq %xmm4, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm0 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: psrlq %xmm1, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,0,1] +; SSE2-NEXT: psrlq %xmm4, %xmm2 +; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm3[0],xmm2[1] +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: psrlq %xmm1, %xmm3 +; SSE2-NEXT: psrlq %xmm4, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm3[0],xmm0[1] +; SSE2-NEXT: xorpd %xmm2, %xmm0 +; SSE2-NEXT: psubq %xmm2, %xmm0 ; SSE2-NEXT: retq ; ; SSE41-LABEL: var_shift_v2i64: @@ -97,19 +96,18 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; ; X32-SSE-LABEL: var_shift_v2i64: ; X32-SSE: # BB#0: -; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648] -; X32-SSE-NEXT: movdqa %xmm2, %xmm4 -; X32-SSE-NEXT: psrlq %xmm3, %xmm4 -; X32-SSE-NEXT: psrlq %xmm1, %xmm2 -; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm2[0],xmm4[1] -; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: psrlq %xmm3, %xmm2 -; X32-SSE-NEXT: psrlq %xmm1, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; X32-SSE-NEXT: xorpd %xmm4, %xmm2 -; X32-SSE-NEXT: psubq %xmm4, %xmm2 -; X32-SSE-NEXT: movdqa %xmm2, %xmm0 +; X32-SSE-NEXT: movdqa %xmm2, %xmm3 +; X32-SSE-NEXT: psrlq %xmm1, %xmm3 +; X32-SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,0,1] +; X32-SSE-NEXT: psrlq %xmm4, %xmm2 +; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm3[0],xmm2[1] +; X32-SSE-NEXT: movdqa %xmm0, %xmm3 +; X32-SSE-NEXT: psrlq %xmm1, %xmm3 +; X32-SSE-NEXT: psrlq %xmm4, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm3[0],xmm0[1] +; X32-SSE-NEXT: xorpd %xmm2, %xmm0 +; X32-SSE-NEXT: psubq %xmm2, %xmm0 ; X32-SSE-NEXT: retl %shift = ashr <2 x i64> %a, %b ret <2 x i64> %shift @@ -119,24 +117,24 @@ define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { ; SSE2-LABEL: var_shift_v4i32: ; SSE2: # BB#0: ; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; SSE2-NEXT: psrlq $32, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: psrad %xmm2, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psrlq $32, %xmm2 +; SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; SSE2-NEXT: movdqa %xmm0, %xmm4 ; SSE2-NEXT: psrad %xmm2, %xmm4 -; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm4[0],xmm3[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] +; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3] ; SSE2-NEXT: pxor %xmm3, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm4 -; SSE2-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] ; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: psrad %xmm4, %xmm5 -; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] +; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3] ; SSE2-NEXT: psrad %xmm1, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm5 = xmm0[0],xmm5[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm5[0,2,2,3] +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm5[0],xmm0[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE2-NEXT: retq ; @@ -207,24 +205,24 @@ define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { ; X32-SSE-LABEL: var_shift_v4i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movdqa %xmm1, %xmm2 -; X32-SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; X32-SSE-NEXT: psrlq $32, %xmm2 ; X32-SSE-NEXT: movdqa %xmm0, %xmm3 ; X32-SSE-NEXT: psrad %xmm2, %xmm3 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2 -; X32-SSE-NEXT: psrlq $32, %xmm2 +; X32-SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X32-SSE-NEXT: movdqa %xmm0, %xmm4 ; X32-SSE-NEXT: psrad %xmm2, %xmm4 -; X32-SSE-NEXT: movsd {{.*#+}} xmm3 = xmm4[0],xmm3[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] +; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3] ; X32-SSE-NEXT: pxor %xmm3, %xmm3 ; X32-SSE-NEXT: movdqa %xmm1, %xmm4 -; X32-SSE-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3] +; X32-SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] ; X32-SSE-NEXT: movdqa %xmm0, %xmm5 ; X32-SSE-NEXT: psrad %xmm4, %xmm5 -; X32-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] +; X32-SSE-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3] ; X32-SSE-NEXT: psrad %xmm1, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm5 = xmm0[0],xmm5[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm5[0,2,2,3] +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm5[0],xmm0[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; X32-SSE-NEXT: retl %shift = ashr <4 x i32> %a, %b @@ -1044,13 +1042,12 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; SSE2-LABEL: constant_shift_v2i64: ; SSE2: # BB#0: ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psrlq $7, %xmm1 -; SSE2-NEXT: psrlq $1, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; SSE2-NEXT: movapd {{.*#+}} xmm0 = [4611686018427387904,72057594037927936] -; SSE2-NEXT: xorpd %xmm0, %xmm1 -; SSE2-NEXT: psubq %xmm0, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: psrlq $1, %xmm1 +; SSE2-NEXT: psrlq $7, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: movapd {{.*#+}} xmm1 = [4611686018427387904,72057594037927936] +; SSE2-NEXT: xorpd %xmm1, %xmm0 +; SSE2-NEXT: psubq %xmm1, %xmm0 ; SSE2-NEXT: retq ; ; SSE41-LABEL: constant_shift_v2i64: @@ -1107,16 +1104,15 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,2147483648,0,2147483648] ; X32-SSE-NEXT: movdqa %xmm1, %xmm2 -; X32-SSE-NEXT: psrlq $7, %xmm2 -; X32-SSE-NEXT: psrlq $1, %xmm1 -; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1] -; X32-SSE-NEXT: movdqa %xmm0, %xmm1 +; X32-SSE-NEXT: psrlq $1, %xmm2 ; X32-SSE-NEXT: psrlq $7, %xmm1 -; X32-SSE-NEXT: psrlq $1, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; X32-SSE-NEXT: xorpd %xmm2, %xmm1 -; X32-SSE-NEXT: psubq %xmm2, %xmm1 -; X32-SSE-NEXT: movdqa %xmm1, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1] +; X32-SSE-NEXT: movdqa %xmm0, %xmm2 +; X32-SSE-NEXT: psrlq $1, %xmm2 +; X32-SSE-NEXT: psrlq $7, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; X32-SSE-NEXT: xorpd %xmm1, %xmm0 +; X32-SSE-NEXT: psubq %xmm1, %xmm0 ; X32-SSE-NEXT: retl %shift = ashr <2 x i64> %a, <i64 1, i64 7> ret <2 x i64> %shift @@ -1126,16 +1122,16 @@ define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind { ; SSE2-LABEL: constant_shift_v4i32: ; SSE2: # BB#0: ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psrad $7, %xmm1 +; SSE2-NEXT: psrad $5, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: psrad $5, %xmm2 -; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] +; SSE2-NEXT: psrad $7, %xmm2 +; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3] ; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: psrad $6, %xmm2 -; SSE2-NEXT: psrad $4, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE2-NEXT: psrad $4, %xmm2 +; SSE2-NEXT: psrad $6, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: retq ; @@ -1192,16 +1188,16 @@ define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind { ; X32-SSE-LABEL: constant_shift_v4i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movdqa %xmm0, %xmm1 -; X32-SSE-NEXT: psrad $7, %xmm1 +; X32-SSE-NEXT: psrad $5, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: psrad $5, %xmm2 -; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] +; X32-SSE-NEXT: psrad $7, %xmm2 +; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3] ; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: psrad $6, %xmm2 -; X32-SSE-NEXT: psrad $4, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; X32-SSE-NEXT: psrad $4, %xmm2 +; X32-SSE-NEXT: psrad $6, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X32-SSE-NEXT: retl %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7> diff --git a/llvm/test/CodeGen/X86/vector-shift-lshr-128.ll b/llvm/test/CodeGen/X86/vector-shift-lshr-128.ll index 05835510d2a..0734b984737 100644 --- a/llvm/test/CodeGen/X86/vector-shift-lshr-128.ll +++ b/llvm/test/CodeGen/X86/vector-shift-lshr-128.ll @@ -20,12 +20,11 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; SSE2-LABEL: var_shift_v2i64: ; SSE2: # BB#0: -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] ; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: psrlq %xmm3, %xmm2 +; SSE2-NEXT: psrlq %xmm1, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] ; SSE2-NEXT: psrlq %xmm1, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE2-NEXT: movapd %xmm2, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] ; SSE2-NEXT: retq ; ; SSE41-LABEL: var_shift_v2i64: @@ -74,12 +73,11 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; ; X32-SSE-LABEL: var_shift_v2i64: ; X32-SSE: # BB#0: -; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] ; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: psrlq %xmm3, %xmm2 +; X32-SSE-NEXT: psrlq %xmm1, %xmm2 +; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] ; X32-SSE-NEXT: psrlq %xmm1, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; X32-SSE-NEXT: movapd %xmm2, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] ; X32-SSE-NEXT: retl %shift = lshr <2 x i64> %a, %b ret <2 x i64> %shift @@ -89,24 +87,24 @@ define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { ; SSE2-LABEL: var_shift_v4i32: ; SSE2: # BB#0: ; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; SSE2-NEXT: psrlq $32, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: psrld %xmm2, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psrlq $32, %xmm2 +; SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; SSE2-NEXT: movdqa %xmm0, %xmm4 ; SSE2-NEXT: psrld %xmm2, %xmm4 -; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm4[0],xmm3[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] +; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3] ; SSE2-NEXT: pxor %xmm3, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm4 -; SSE2-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] ; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: psrld %xmm4, %xmm5 -; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] +; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3] ; SSE2-NEXT: psrld %xmm1, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm5 = xmm0[0],xmm5[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm5[0,2,2,3] +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm5[0],xmm0[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE2-NEXT: retq ; @@ -177,24 +175,24 @@ define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { ; X32-SSE-LABEL: var_shift_v4i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movdqa %xmm1, %xmm2 -; X32-SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; X32-SSE-NEXT: psrlq $32, %xmm2 ; X32-SSE-NEXT: movdqa %xmm0, %xmm3 ; X32-SSE-NEXT: psrld %xmm2, %xmm3 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2 -; X32-SSE-NEXT: psrlq $32, %xmm2 +; X32-SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X32-SSE-NEXT: movdqa %xmm0, %xmm4 ; X32-SSE-NEXT: psrld %xmm2, %xmm4 -; X32-SSE-NEXT: movsd {{.*#+}} xmm3 = xmm4[0],xmm3[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] +; X32-SSE-NEXT: movsd {{.*#+}} xmm4 = xmm3[0],xmm4[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3] ; X32-SSE-NEXT: pxor %xmm3, %xmm3 ; X32-SSE-NEXT: movdqa %xmm1, %xmm4 -; X32-SSE-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3] +; X32-SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] ; X32-SSE-NEXT: movdqa %xmm0, %xmm5 ; X32-SSE-NEXT: psrld %xmm4, %xmm5 -; X32-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] +; X32-SSE-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3] ; X32-SSE-NEXT: psrld %xmm1, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm5 = xmm0[0],xmm5[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm5[0,2,2,3] +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm5[0],xmm0[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; X32-SSE-NEXT: retl %shift = lshr <4 x i32> %a, %b @@ -821,10 +819,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; SSE2-LABEL: constant_shift_v2i64: ; SSE2: # BB#0: ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psrlq $7, %xmm1 -; SSE2-NEXT: psrlq $1, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: psrlq $1, %xmm1 +; SSE2-NEXT: psrlq $7, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSE2-NEXT: retq ; ; SSE41-LABEL: constant_shift_v2i64: @@ -872,10 +869,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; X32-SSE-LABEL: constant_shift_v2i64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movdqa %xmm0, %xmm1 -; X32-SSE-NEXT: psrlq $7, %xmm1 -; X32-SSE-NEXT: psrlq $1, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; X32-SSE-NEXT: movapd %xmm1, %xmm0 +; X32-SSE-NEXT: psrlq $1, %xmm1 +; X32-SSE-NEXT: psrlq $7, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; X32-SSE-NEXT: retl %shift = lshr <2 x i64> %a, <i64 1, i64 7> ret <2 x i64> %shift @@ -885,16 +881,16 @@ define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind { ; SSE2-LABEL: constant_shift_v4i32: ; SSE2: # BB#0: ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psrld $7, %xmm1 +; SSE2-NEXT: psrld $5, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: psrld $5, %xmm2 -; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] +; SSE2-NEXT: psrld $7, %xmm2 +; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3] ; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: psrld $6, %xmm2 -; SSE2-NEXT: psrld $4, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE2-NEXT: psrld $4, %xmm2 +; SSE2-NEXT: psrld $6, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: retq ; @@ -951,16 +947,16 @@ define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind { ; X32-SSE-LABEL: constant_shift_v4i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movdqa %xmm0, %xmm1 -; X32-SSE-NEXT: psrld $7, %xmm1 +; X32-SSE-NEXT: psrld $5, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: psrld $5, %xmm2 -; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] +; X32-SSE-NEXT: psrld $7, %xmm2 +; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3] ; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: psrld $6, %xmm2 -; X32-SSE-NEXT: psrld $4, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; X32-SSE-NEXT: psrld $4, %xmm2 +; X32-SSE-NEXT: psrld $6, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X32-SSE-NEXT: retl %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7> diff --git a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll index c125a3756a6..252c4d03b68 100644 --- a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll +++ b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll @@ -20,12 +20,11 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; SSE2-LABEL: var_shift_v2i64: ; SSE2: # BB#0: -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] ; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: psllq %xmm3, %xmm2 +; SSE2-NEXT: psllq %xmm1, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] ; SSE2-NEXT: psllq %xmm1, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE2-NEXT: movapd %xmm2, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] ; SSE2-NEXT: retq ; ; SSE41-LABEL: var_shift_v2i64: @@ -72,12 +71,11 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; ; X32-SSE-LABEL: var_shift_v2i64: ; X32-SSE: # BB#0: -; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] ; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: psllq %xmm3, %xmm2 +; X32-SSE-NEXT: psllq %xmm1, %xmm2 +; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] ; X32-SSE-NEXT: psllq %xmm1, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; X32-SSE-NEXT: movapd %xmm2, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] ; X32-SSE-NEXT: retl %shift = shl <2 x i64> %a, %b ret <2 x i64> %shift @@ -762,10 +760,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; SSE2-LABEL: constant_shift_v2i64: ; SSE2: # BB#0: ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psllq $7, %xmm1 -; SSE2-NEXT: psllq $1, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: psllq $1, %xmm1 +; SSE2-NEXT: psllq $7, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSE2-NEXT: retq ; ; SSE41-LABEL: constant_shift_v2i64: @@ -811,10 +808,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; X32-SSE-LABEL: constant_shift_v2i64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movdqa %xmm0, %xmm1 -; X32-SSE-NEXT: psllq $7, %xmm1 -; X32-SSE-NEXT: psllq $1, %xmm0 -; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] -; X32-SSE-NEXT: movapd %xmm1, %xmm0 +; X32-SSE-NEXT: psllq $1, %xmm1 +; X32-SSE-NEXT: psllq $7, %xmm0 +; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; X32-SSE-NEXT: retl %shift = shl <2 x i64> %a, <i64 1, i64 7> ret <2 x i64> %shift diff --git a/llvm/test/CodeGen/X86/vector-trunc-math.ll b/llvm/test/CodeGen/X86/vector-trunc-math.ll index 866fb8ec760..a3044b65ce4 100644 --- a/llvm/test/CodeGen/X86/vector-trunc-math.ll +++ b/llvm/test/CodeGen/X86/vector-trunc-math.ll @@ -52,22 +52,21 @@ define <4 x i32> @trunc_add_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_add_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_add_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: paddq %xmm4, %xmm0 -; SSE-NEXT: paddq %xmm5, %xmm1 ; SSE-NEXT: paddq %xmm6, %xmm2 ; SSE-NEXT: paddq %xmm7, %xmm3 -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE-NEXT: paddq %xmm4, %xmm0 +; SSE-NEXT: paddq %xmm5, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: movapd %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_v8i64_v8i16: @@ -491,19 +490,18 @@ define <4 x i32> @trunc_add_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_add_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_add_const_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: paddw {{.*}}(%rip), %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] +; SSE-NEXT: paddw {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_const_v8i64_v8i16: @@ -837,22 +835,21 @@ define <4 x i32> @trunc_sub_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_sub_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_sub_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: psubq %xmm4, %xmm0 -; SSE-NEXT: psubq %xmm5, %xmm1 ; SSE-NEXT: psubq %xmm6, %xmm2 ; SSE-NEXT: psubq %xmm7, %xmm3 -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE-NEXT: psubq %xmm4, %xmm0 +; SSE-NEXT: psubq %xmm5, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: movapd %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_v8i64_v8i16: @@ -1673,30 +1670,29 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_mul_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_mul_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm7[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm7 = xmm7[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] +; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[0,1,0,2,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1] ; SSE-NEXT: movsd {{.*#+}} xmm6 = xmm4[0],xmm6[1] -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: pmullw %xmm6, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] +; SSE-NEXT: pmullw %xmm6, %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_v8i64_v8i16: @@ -2367,19 +2363,18 @@ define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_mul_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_mul_const_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: pmullw {{.*}}(%rip), %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] +; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_const_v8i64_v8i16: @@ -2858,22 +2853,21 @@ define <4 x i32> @trunc_and_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_and_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pand %xmm4, %xmm0 -; SSE-NEXT: pand %xmm5, %xmm1 ; SSE-NEXT: pand %xmm6, %xmm2 ; SSE-NEXT: pand %xmm7, %xmm3 -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE-NEXT: pand %xmm4, %xmm0 +; SSE-NEXT: pand %xmm5, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: movapd %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_v8i64_v8i16: @@ -3228,19 +3222,18 @@ define <4 x i32> @trunc_and_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_and_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_and_const_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: andpd {{.*}}(%rip), %xmm2 -; SSE-NEXT: movapd %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] +; SSE-NEXT: andpd {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_const_v8i64_v8i16: @@ -3572,22 +3565,21 @@ define <4 x i32> @trunc_xor_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_xor_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pxor %xmm4, %xmm0 -; SSE-NEXT: pxor %xmm5, %xmm1 ; SSE-NEXT: pxor %xmm6, %xmm2 ; SSE-NEXT: pxor %xmm7, %xmm3 -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE-NEXT: pxor %xmm4, %xmm0 +; SSE-NEXT: pxor %xmm5, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: movapd %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_v8i64_v8i16: @@ -3942,19 +3934,18 @@ define <4 x i32> @trunc_xor_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_xor_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_xor_const_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: xorpd {{.*}}(%rip), %xmm2 -; SSE-NEXT: movapd %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] +; SSE-NEXT: xorpd {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_const_v8i64_v8i16: @@ -4286,22 +4277,21 @@ define <4 x i32> @trunc_or_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_or_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: por %xmm4, %xmm0 -; SSE-NEXT: por %xmm5, %xmm1 ; SSE-NEXT: por %xmm6, %xmm2 ; SSE-NEXT: por %xmm7, %xmm3 -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE-NEXT: por %xmm4, %xmm0 +; SSE-NEXT: por %xmm5, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: movapd %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_v8i64_v8i16: @@ -4656,19 +4646,18 @@ define <4 x i32> @trunc_or_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_or_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_or_const_v8i64_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE-NEXT: orpd {{.*}}(%rip), %xmm2 -; SSE-NEXT: movapd %xmm2, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] +; SSE-NEXT: orpd {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_const_v8i64_v8i16: diff --git a/llvm/test/CodeGen/X86/vector-trunc.ll b/llvm/test/CodeGen/X86/vector-trunc.ll index 176a9eb6c98..51797612cdc 100644 --- a/llvm/test/CodeGen/X86/vector-trunc.ll +++ b/llvm/test/CodeGen/X86/vector-trunc.ll @@ -173,34 +173,32 @@ entry: define <8 x i16> @trunc8i64_8i16(<8 x i64> %a) { ; SSE2-LABEL: trunc8i64_8i16: ; SSE2: # BB#0: # %entry -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE2-NEXT: movapd %xmm2, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] ; SSE2-NEXT: retq ; ; SSSE3-LABEL: trunc8i64_8i16: ; SSSE3: # BB#0: # %entry -; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSSE3-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSSE3-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSSE3-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSSE3-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSSE3-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSSE3-NEXT: movapd %xmm2, %xmm0 +; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] ; SSSE3-NEXT: retq ; ; SSE41-LABEL: trunc8i64_8i16: @@ -1485,34 +1483,32 @@ entry: define <8 x i16> @trunc2x4i64_8i16(<4 x i64> %a, <4 x i64> %b) { ; SSE2-LABEL: trunc2x4i64_8i16: ; SSE2: # BB#0: # %entry -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSE2-NEXT: movapd %xmm2, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] ; SSE2-NEXT: retq ; ; SSSE3-LABEL: trunc2x4i64_8i16: ; SSSE3: # BB#0: # %entry -; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSSE3-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7] -; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSSE3-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSSE3-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7] +; SSSE3-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] +; SSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7] +; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSSE3-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] -; SSSE3-NEXT: movapd %xmm2, %xmm0 +; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1] ; SSSE3-NEXT: retq ; ; SSE41-LABEL: trunc2x4i64_8i16: diff --git a/llvm/test/CodeGen/X86/vshift-4.ll b/llvm/test/CodeGen/X86/vshift-4.ll index 5d486e79405..a47f5641972 100644 --- a/llvm/test/CodeGen/X86/vshift-4.ll +++ b/llvm/test/CodeGen/X86/vshift-4.ll @@ -30,22 +30,22 @@ define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind { ; X32-LABEL: shift1b: ; X32: # BB#0: # %entry ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1] -; X32-NEXT: movdqa %xmm0, %xmm3 -; X32-NEXT: psllq %xmm2, %xmm3 +; X32-NEXT: movdqa %xmm0, %xmm2 +; X32-NEXT: psllq %xmm1, %xmm2 +; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] ; X32-NEXT: psllq %xmm1, %xmm0 -; X32-NEXT: movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1] -; X32-NEXT: movapd %xmm3, (%eax) +; X32-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; X32-NEXT: movapd %xmm0, (%eax) ; X32-NEXT: retl ; ; X64-LABEL: shift1b: ; X64: # BB#0: # %entry -; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1] -; X64-NEXT: movdqa %xmm0, %xmm3 -; X64-NEXT: psllq %xmm2, %xmm3 +; X64-NEXT: movdqa %xmm0, %xmm2 +; X64-NEXT: psllq %xmm1, %xmm2 +; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] ; X64-NEXT: psllq %xmm1, %xmm0 -; X64-NEXT: movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1] -; X64-NEXT: movapd %xmm3, (%rdi) +; X64-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; X64-NEXT: movapd %xmm0, (%rdi) ; X64-NEXT: retq entry: %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1> diff --git a/llvm/test/CodeGen/X86/x86-shifts.ll b/llvm/test/CodeGen/X86/x86-shifts.ll index 8a51863bd1b..9ab54891254 100644 --- a/llvm/test/CodeGen/X86/x86-shifts.ll +++ b/llvm/test/CodeGen/X86/x86-shifts.ll @@ -231,10 +231,10 @@ define <2 x i64> @shr2_nosplat(<2 x i64> %A) nounwind { ; ; X64-LABEL: shr2_nosplat: ; X64: # BB#0: # %entry -; X64-NEXT: movdqa %xmm0, %xmm1 -; X64-NEXT: psrlq $1, %xmm1 ; X64-NEXT: movdqa %xmm0, %xmm2 ; X64-NEXT: psrlq $8, %xmm2 +; X64-NEXT: movdqa %xmm0, %xmm1 +; X64-NEXT: psrlq $1, %xmm1 ; X64-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; X64-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1] ; X64-NEXT: xorpd %xmm0, %xmm1 |
