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authorPeter Smith <peter.smith@linaro.org>2018-10-08 09:38:28 +0000
committerPeter Smith <peter.smith@linaro.org>2018-10-08 09:38:28 +0000
commit6f36cd4d76c65796b695df1a34c501ac3aa05229 (patch)
treef7c9bbd09bc10453301a0261273f23a0a7605d17 /llvm/test
parent9ecdac8ee0884b02e3aff87bf61472c207824ef4 (diff)
downloadbcm5719-llvm-6f36cd4d76c65796b695df1a34c501ac3aa05229.tar.gz
bcm5719-llvm-6f36cd4d76c65796b695df1a34c501ac3aa05229.zip
[ARM] Account for implicit IT when calculating inline asm size
When deciding if it is safe to optimize a conditional branch to a CBZ or CBNZ the offsets of the BasicBlocks from the start of the function are estimated. For inline assembly the generic getInlineAsmLength() function is used to get a worst case estimate of the inline assembly by multiplying the number of instructions by the max instruction size of 4 bytes. This unfortunately doesn't take into account the generation of Thumb implicit IT instructions. In edge cases such as when all the instructions in the block are 4-bytes in size and there is an implicit IT then the size is underestimated. This can cause an out of range CBZ or CBNZ to be generated. The patch takes a conservative approach and assumes that every instruction in the inline assembly block may have an implicit IT. Fixes pr31805 Differential Revision: https://reviews.llvm.org/D52834 llvm-svn: 343960
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/ARM/cbz-implicit-it-range.ll47
1 files changed, 47 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/cbz-implicit-it-range.ll b/llvm/test/CodeGen/ARM/cbz-implicit-it-range.ll
new file mode 100644
index 00000000000..b553a9ad6df
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cbz-implicit-it-range.ll
@@ -0,0 +1,47 @@
+;RUN: llc -O2 -mtriple=thumbv7a-linux-gnueabihf -arm-implicit-it=always %s -o - | FileCheck %s
+;RUN: llc -O2 -mtriple=thumbv7a-linux-gnueabihf -no-integrated-as %s -o - | FileCheck %s
+
+; Check that we do not produce a CBZ instruction to jump over the inline
+; assembly as the distance is too far if the implicit IT instructions are
+; added.
+
+define void @f0(i32 %p1, i32 %p2, i32 %p3) nounwind {
+entry:
+ %cmp = icmp eq i32 %p1, 0
+ br i1 %cmp, label %if.else, label %if.then
+
+if.then:
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ tail call void asm sideeffect "movseq r0, #0\0A", ""()
+ br label %if.end
+
+if.else:
+ tail call void asm sideeffect "nop\0A", ""()
+ br label %if.end
+
+if.end:
+ ret void
+}
+; CHECK-LABEL: f0:
+; CHECK: beq .LBB0_{{[0-9]+}}
+
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