[SystemZ] Add RISBLG and RISBHG instruction definitions

The next patch will make use of RISBLG for codegen.

llvm-svn: 187490

4 files changed, 124 insertions, 0 deletions

diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index cf26b653b2a..fa30bd31a0e 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -4957,6 +4957,48 @@
 # CHECK: risbg %r4, %r5, 6, 7, 8
 0xec 0x45 0x06 0x07 0x08 0x55
 
+# CHECK: risbhg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x5d
+
+# CHECK: risbhg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x5d
+
+# CHECK: risbhg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x5d
+
+# CHECK: risbhg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x5d
+
+# CHECK: risblg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x51
+
+# CHECK: risblg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x51
+
+# CHECK: risblg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x51
+
+# CHECK: risblg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x51
+
 # CHECK: rnsbg %r0, %r0, 0, 0, 0
 0xec 0x00 0x00 0x00 0x00 0x54
 
diff --git a/llvm/test/MC/SystemZ/insn-bad-z196.s b/llvm/test/MC/SystemZ/insn-bad-z196.s
index a5e21894a3d..ec90c89b4c2 100644
--- a/llvm/test/MC/SystemZ/insn-bad-z196.s
+++ b/llvm/test/MC/SystemZ/insn-bad-z196.s
@@ -75,6 +75,46 @@
 	locr	%r0,%r0,16
 
 #CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,256,0,0
+
+	risbhg	%r0,%r0,0,0,-1
+	risbhg	%r0,%r0,0,0,64
+	risbhg	%r0,%r0,0,-1,0
+	risbhg	%r0,%r0,0,256,0
+	risbhg	%r0,%r0,-1,0,0
+	risbhg	%r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,256,0,0
+
+	risblg	%r0,%r0,0,0,-1
+	risblg	%r0,%r0,0,0,64
+	risblg	%r0,%r0,0,-1,0
+	risblg	%r0,%r0,0,256,0
+	risblg	%r0,%r0,-1,0,0
+	risblg	%r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
 #CHECK: sllk	%r0,%r0,-524289
 #CHECK: error: invalid operand
 #CHECK: sllk	%r0,%r0,524288
diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s
index f8900566778..eab11d1dd24 100644
--- a/llvm/test/MC/SystemZ/insn-bad.s
+++ b/llvm/test/MC/SystemZ/insn-bad.s
@@ -2176,6 +2176,16 @@
 	risbg	%r0,%r0,-1,0,0
 	risbg	%r0,%r0,256,0,0
 
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: risbhg	%r1, %r2, 0, 0, 0
+
+	risbhg	%r1, %r2, 0, 0, 0
+
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: risblg	%r1, %r2, 0, 0, 0
+
+	risblg	%r1, %r2, 0, 0, 0
+
 #CHECK: error: invalid operand
 #CHECK: rnsbg	%r0,%r0,0,0,-1
 #CHECK: error: invalid operand
diff --git a/llvm/test/MC/SystemZ/insn-good-z196.s b/llvm/test/MC/SystemZ/insn-good-z196.s
index f5213b910b9..5f7c27785d7 100644
--- a/llvm/test/MC/SystemZ/insn-good-z196.s
+++ b/llvm/test/MC/SystemZ/insn-good-z196.s
@@ -337,6 +337,38 @@
 	ork	%r15,%r0,%r0
 	ork	%r7,%r8,%r9
 
+#CHECK: risbhg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x5d]
+#CHECK: risbhg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x5d]
+#CHECK: risbhg	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x5d]
+#CHECK: risbhg	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x5d]
+
+	risbhg	%r0,%r0,0,0,0
+	risbhg	%r0,%r0,0,0,63
+	risbhg	%r0,%r0,0,255,0
+	risbhg	%r0,%r0,255,0,0
+	risbhg	%r0,%r15,0,0,0
+	risbhg	%r15,%r0,0,0,0
+	risbhg	%r4,%r5,6,7,8
+
+#CHECK: risblg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x51]
+#CHECK: risblg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x51]
+#CHECK: risblg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x51]
+#CHECK: risblg	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x51]
+#CHECK: risblg	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x51]
+#CHECK: risblg	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x51]
+#CHECK: risblg	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x51]
+
+	risblg	%r0,%r0,0,0,0
+	risblg	%r0,%r0,0,0,63
+	risblg	%r0,%r0,0,255,0
+	risblg	%r0,%r0,255,0,0
+	risblg	%r0,%r15,0,0,0
+	risblg	%r15,%r0,0,0,0
+	risblg	%r4,%r5,6,7,8
+
 #CHECK: sgrk	%r0, %r0, %r0           # encoding: [0xb9,0xe9,0x00,0x00]
 #CHECK: sgrk	%r0, %r0, %r15          # encoding: [0xb9,0xe9,0xf0,0x00]
 #CHECK: sgrk	%r0, %r15, %r0          # encoding: [0xb9,0xe9,0x00,0x0f]