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| author | Hal Finkel <hfinkel@anl.gov> | 2015-01-09 01:34:30 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2015-01-09 01:34:30 +0000 |
| commit | 6c39269a4c5617fab7d1c36c372db82e51e4c925 (patch) | |
| tree | ca02cf0f29fef057258efd288b2a21d4688913bd /llvm/test | |
| parent | 0ce7f372e5016999b3a56cb2a0eb8784cd4179af (diff) | |
| download | bcm5719-llvm-6c39269a4c5617fab7d1c36c372db82e51e4c925.tar.gz bcm5719-llvm-6c39269a4c5617fab7d1c36c372db82e51e4c925.zip | |
[PowerPC] Fold [sz]ext with fp_to_int lowering where possible
On modern cores with lfiw[az]x, we can fold a sign or zero extension from i32
to i64 into the load necessary for an i64 -> fp conversion.
llvm-svn: 225493
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fp-to-int-ext.ll | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-ext.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-ext.ll new file mode 100644 index 00000000000..bfacd89ca1a --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fp-to-int-ext.ll @@ -0,0 +1,69 @@ +; RUN: llc -mcpu=a2 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define double @foo1(i32* %x) #0 { +entry: + %0 = load i32* %x, align 4 + %conv = sext i32 %0 to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; CHECK-LABEL: @foo1 +; CHECK: lfiwax [[REG1:[0-9]+]], 0, 3 +; CHECK: fcfid 1, [[REG1]] +; CHECK: blr +} + +define double @foo2(i32* %x) #0 { +entry: + %0 = load i32* %x, align 4 + %conv = zext i32 %0 to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; CHECK-LABEL: @foo2 +; CHECK: lfiwzx [[REG1:[0-9]+]], 0, 3 +; CHECK: fcfid 1, [[REG1]] +; CHECK: blr +} + +define double @foo3(i32* %x) #0 { +entry: + %0 = load i32* %x, align 4 + %1 = add i32 %0, 8 + %conv = zext i32 %1 to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; CHECK-LABEL: @foo3 +; CHECK-DAG: lwz [[REG1:[0-9]+]], 0(3) +; CHECK-DAG: addi [[REG3:[0-9]+]], 1, +; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], 8 +; CHECK-DAG: stw [[REG2]], +; CHECK: lfiwzx [[REG4:[0-9]+]], 0, [[REG3]] +; CHECK: fcfid 1, [[REG4]] +; CHECK: blr +} + +define double @foo4(i32* %x) #0 { +entry: + %0 = load i32* %x, align 4 + %1 = add i32 %0, 8 + %conv = sext i32 %1 to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; CHECK-LABEL: @foo4 +; CHECK-DAG: lwz [[REG1:[0-9]+]], 0(3) +; CHECK-DAG: addi [[REG3:[0-9]+]], 1, +; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], 8 +; CHECK-DAG: stw [[REG2]], +; CHECK: lfiwax [[REG4:[0-9]+]], 0, [[REG3]] +; CHECK: fcfid 1, [[REG4]] +; CHECK: blr +} + +attributes #0 = { nounwind } + |
