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authorDan Gohman <gohman@apple.com>2010-01-09 02:13:55 +0000
committerDan Gohman <gohman@apple.com>2010-01-09 02:13:55 +0000
commit6bd3ef82ff62e46aba31dc9c748552925376fa76 (patch)
treec765d2fb59322ec17a412054f16ce89219946ae4 /llvm/test
parent003143c582d7197661f5435f94a78c607096f651 (diff)
downloadbcm5719-llvm-6bd3ef82ff62e46aba31dc9c748552925376fa76.tar.gz
bcm5719-llvm-6bd3ef82ff62e46aba31dc9c748552925376fa76.zip
Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode
really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/X86/vec_cast.ll48
-rw-r--r--llvm/test/CodeGen/X86/vec_ext_inreg.ll1
2 files changed, 49 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/vec_cast.ll b/llvm/test/CodeGen/X86/vec_cast.ll
new file mode 100644
index 00000000000..1f899b3c20a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec_cast.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86-64 -disable-mmx
+
+define <8 x i32> @a(<8 x i16> %a) nounwind {
+ %c = sext <8 x i16> %a to <8 x i32>
+ ret <8 x i32> %c
+}
+
+define <3 x i32> @b(<3 x i16> %a) nounwind {
+ %c = sext <3 x i16> %a to <3 x i32>
+ ret <3 x i32> %c
+}
+
+define <1 x i32> @c(<1 x i16> %a) nounwind {
+ %c = sext <1 x i16> %a to <1 x i32>
+ ret <1 x i32> %c
+}
+
+define <8 x i32> @d(<8 x i16> %a) nounwind {
+ %c = zext <8 x i16> %a to <8 x i32>
+ ret <8 x i32> %c
+}
+
+define <3 x i32> @e(<3 x i16> %a) nounwind {
+ %c = zext <3 x i16> %a to <3 x i32>
+ ret <3 x i32> %c
+}
+
+define <1 x i32> @f(<1 x i16> %a) nounwind {
+ %c = zext <1 x i16> %a to <1 x i32>
+ ret <1 x i32> %c
+}
+
+; TODO: Legalize doesn't yet handle this.
+;define <8 x i16> @g(<8 x i32> %a) nounwind {
+; %c = trunc <8 x i32> %a to <8 x i16>
+; ret <8 x i16> %c
+;}
+
+define <3 x i16> @h(<3 x i32> %a) nounwind {
+ %c = trunc <3 x i32> %a to <3 x i16>
+ ret <3 x i16> %c
+}
+
+define <1 x i16> @i(<1 x i32> %a) nounwind {
+ %c = trunc <1 x i32> %a to <1 x i16>
+ ret <1 x i16> %c
+}
diff --git a/llvm/test/CodeGen/X86/vec_ext_inreg.ll b/llvm/test/CodeGen/X86/vec_ext_inreg.ll
index 02b16a79f4a..8d2a3c31aed 100644
--- a/llvm/test/CodeGen/X86/vec_ext_inreg.ll
+++ b/llvm/test/CodeGen/X86/vec_ext_inreg.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86-64 -disable-mmx
define <8 x i32> @a(<8 x i32> %a) nounwind {
%b = trunc <8 x i32> %a to <8 x i16>
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