[x86] regenerate complete checks; NFC

D42265 will improve something here, but it's not obvious how without more checks.

llvm-svn: 322960

1 files changed, 51 insertions, 30 deletions

diff --git a/llvm/test/CodeGen/X86/3addr-or.ll b/llvm/test/CodeGen/X86/3addr-or.ll
index 76fabbf0f6a..a31c4f2cf60 100644
--- a/llvm/test/CodeGen/X86/3addr-or.ll
+++ b/llvm/test/CodeGen/X86/3addr-or.ll
@@ -1,61 +1,82 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 ; rdar://7527734
 
-define i32 @test1(i32 %x) nounwind readnone ssp {
-entry:
+define i32 @test1(i32 %x) nounwind ssp {
 ; CHECK-LABEL: test1:
-; CHECK: leal 3(%rdi), %eax
-  %0 = shl i32 %x, 5                              ; <i32> [#uses=1]
-  %1 = or i32 %0, 3                               ; <i32> [#uses=1]
-  ret i32 %1
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def %edi killed %edi def %rdi
+; CHECK-NEXT:    shll $5, %edi
+; CHECK-NEXT:    leal 3(%rdi), %eax
+; CHECK-NEXT:    retq
+  %t0 = shl i32 %x, 5
+  %t1 = or i32 %t0, 3
+  ret i32 %t1
 }
 
 define i64 @test2(i8 %A, i8 %B) nounwind {
 ; CHECK-LABEL: test2:
-; CHECK: shrq $4
-; CHECK-NOT: movq
-; CHECK-NOT: orq
-; CHECK: leaq
-; CHECK: ret
-  %C = zext i8 %A to i64                          ; <i64> [#uses=1]
-  %D = shl i64 %C, 4                              ; <i64> [#uses=1]
-  %E = and i64 %D, 48                             ; <i64> [#uses=1]
-  %F = zext i8 %B to i64                          ; <i64> [#uses=1]
-  %G = lshr i64 %F, 4                             ; <i64> [#uses=1]
-  %H = or i64 %G, %E                              ; <i64> [#uses=1]
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def %esi killed %esi def %rsi
+; CHECK-NEXT:    # kill: def %edi killed %edi def %rdi
+; CHECK-NEXT:    shll $4, %edi
+; CHECK-NEXT:    andl $48, %edi
+; CHECK-NEXT:    andl $240, %esi
+; CHECK-NEXT:    shrq $4, %rsi
+; CHECK-NEXT:    leaq (%rsi,%rdi), %rax
+; CHECK-NEXT:    retq
+  %C = zext i8 %A to i64
+  %D = shl i64 %C, 4
+  %E = and i64 %D, 48
+  %F = zext i8 %B to i64
+  %G = lshr i64 %F, 4
+  %H = or i64 %G, %E
   ret i64 %H
 }
 
 ;; Test that OR is only emitted as LEA, not as ADD.
 
-define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
-entry:
 ; No reason to emit an add here, should be an or.
+define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
 ; CHECK-LABEL: test3:
-; CHECK: orl $3, %edi
-  %0 = shl i32 %x, 5
-  %1 = or i32 %0, 3
-  store i32 %1, i32* %P
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shll $5, %edi
+; CHECK-NEXT:    orl $3, %edi
+; CHECK-NEXT:    movl %edi, (%rsi)
+; CHECK-NEXT:    retq
+  %t0 = shl i32 %x, 5
+  %t1 = or i32 %t0, 3
+  store i32 %t1, i32* %P
   ret void
 }
 
 define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp {
-entry:
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def %esi killed %esi def %rsi
+; CHECK-NEXT:    # kill: def %edi killed %edi def %rdi
+; CHECK-NEXT:    andl $6, %edi
+; CHECK-NEXT:    andl $16, %esi
+; CHECK-NEXT:    leal (%rsi,%rdi), %eax
+; CHECK-NEXT:    retq
   %and = and i32 %a, 6
   %and2 = and i32 %b, 16
   %or = or i32 %and2, %and
   ret i32 %or
-; CHECK-LABEL: test4:
-; CHECK: leal	(%rsi,%rdi), %eax
 }
 
 define void @test5(i32 %a, i32 %b, i32* nocapture %P) nounwind ssp {
-entry:
+; CHECK-LABEL: test5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andl $6, %edi
+; CHECK-NEXT:    andl $16, %esi
+; CHECK-NEXT:    orl %edi, %esi
+; CHECK-NEXT:    movl %esi, (%rdx)
+; CHECK-NEXT:    retq
   %and = and i32 %a, 6
   %and2 = and i32 %b, 16
   %or = or i32 %and2, %and
   store i32 %or, i32* %P, align 4
   ret void
-; CHECK-LABEL: test5:
-; CHECK: orl
 }
+