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| author | Craig Topper <craig.topper@gmail.com> | 2016-12-06 08:08:04 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-12-06 08:08:04 +0000 |
| commit | 683470bf1bff8f28fdbadd54f37c629956519edf (patch) | |
| tree | e514b02ff0ec4ffa6b993730a8f908c75db03a08 /llvm/test | |
| parent | 125939ff65b8f5832342dbccb590cf111f9fff27 (diff) | |
| download | bcm5719-llvm-683470bf1bff8f28fdbadd54f37c629956519edf.tar.gz bcm5719-llvm-683470bf1bff8f28fdbadd54f37c629956519edf.zip | |
[X86] Remove bad pattern that caused 128-bit loads being used by scalar sqrt/rcp/rsqrt intrinsics to select the memory form of the corresponding instruction and violate the semantics of the intrinsic.
The intrinsics are supposed to pass the upper bits straight through to their output register. This means we need to make sure we still perform the 128-bit load to get those upper bits to pass to give to the instruction since the memory form of the instruction only reads 32 or 64 bits.
llvm-svn: 288781
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll b/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll index 22f25c19b0b..747bee127e3 100644 --- a/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll +++ b/llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll @@ -1504,7 +1504,8 @@ define <2 x double> @test_x86_sse2_sqrt_sd_vec_load(<2 x double>* %a0) { ; SSE-LABEL: test_x86_sse2_sqrt_sd_vec_load: ; SSE: ## BB#0: ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04] -; SSE-NEXT: sqrtsd (%eax), %xmm0 ## encoding: [0xf2,0x0f,0x51,0x00] +; SSE-NEXT: movaps (%eax), %xmm0 ## encoding: [0x0f,0x28,0x00] +; SSE-NEXT: sqrtsd %xmm0, %xmm0 ## encoding: [0xf2,0x0f,0x51,0xc0] ; SSE-NEXT: retl ## encoding: [0xc3] ; ; AVX2-LABEL: test_x86_sse2_sqrt_sd_vec_load: |
