test/CodeGen/R600: Add some basic tests v6

llvm-svn: 160273

27 files changed, 212 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/R600/fadd.ll b/llvm/test/CodeGen/R600/fadd.ll
new file mode 100644
index 00000000000..874fcc6f43e
--- /dev/null
+++ b/llvm/test/CodeGen/R600/fadd.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = fadd float %r0, %r1
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
diff --git a/llvm/test/CodeGen/R600/fadd.ll.check b/llvm/test/CodeGen/R600/fadd.ll.check
new file mode 100644
index 00000000000..886082f2262
--- /dev/null
+++ b/llvm/test/CodeGen/R600/fadd.ll.check
diff --git a/llvm/test/CodeGen/R600/fmul.ll b/llvm/test/CodeGen/R600/fmul.ll
new file mode 100644
index 00000000000..28bc4d8008e
--- /dev/null
+++ b/llvm/test/CodeGen/R600/fmul.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = fmul float %r0, %r1
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
diff --git a/llvm/test/CodeGen/R600/fmul.ll.check b/llvm/test/CodeGen/R600/fmul.ll.check
new file mode 100644
index 00000000000..9ba36ccb741
--- /dev/null
+++ b/llvm/test/CodeGen/R600/fmul.ll.check
diff --git a/llvm/test/CodeGen/R600/fsub.ll b/llvm/test/CodeGen/R600/fsub.ll
new file mode 100644
index 00000000000..8e431280fca
--- /dev/null
+++ b/llvm/test/CodeGen/R600/fsub.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = fsub float %r0, %r1
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
diff --git a/llvm/test/CodeGen/R600/fsub.ll.check b/llvm/test/CodeGen/R600/fsub.ll.check
new file mode 100644
index 00000000000..79993541ce6
--- /dev/null
+++ b/llvm/test/CodeGen/R600/fsub.ll.check
diff --git a/llvm/test/CodeGen/R600/lit.local.cfg b/llvm/test/CodeGen/R600/lit.local.cfg
new file mode 100644
index 00000000000..79fc2ba362f
--- /dev/null
+++ b/llvm/test/CodeGen/R600/lit.local.cfg
@@ -0,0 +1,13 @@
+config.suffixes = ['.ll', '.c', '.cpp']
+
+def getRoot(config):
+    if not config.parent:
+        return config
+    return getRoot(config.parent)
+
+root = getRoot(config)
+
+targets = set(root.targets_to_build.split())
+if not 'AMDGPU' in targets:
+    config.unsupported = True
+
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.cos.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.cos.ll
new file mode 100644
index 00000000000..8db95638aeb
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.cos.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.cos( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.cos(float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check b/llvm/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check
new file mode 100644
index 00000000000..ef1389b27a3
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.floor.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.floor.ll
new file mode 100644
index 00000000000..729a7834773
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.floor.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.floor( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.floor(float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check b/llvm/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check
new file mode 100644
index 00000000000..324c10d94c8
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.mul.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.mul.ll
new file mode 100644
index 00000000000..3c995c924f8
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.mul.ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = call float @llvm.AMDGPU.mul( float %r0, float %r1)
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.mul(float ,float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check b/llvm/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check
new file mode 100644
index 00000000000..0a79cbaf263
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.pow.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.pow.ll
new file mode 100644
index 00000000000..b692081c13e
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.pow.ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = call float @llvm.AMDGPU.pow( float %r0, float %r1)
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.pow(float ,float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check b/llvm/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check
new file mode 100644
index 00000000000..94af645419b
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
new file mode 100644
index 00000000000..3efae497416
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.rcp( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.rcp(float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check b/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check
new file mode 100644
index 00000000000..75fe90c5189
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.sin.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.sin.ll
new file mode 100644
index 00000000000..6a427b5d1af
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.sin.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.sin( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.sin(float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check b/llvm/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check
new file mode 100644
index 00000000000..53535543a94
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
new file mode 100644
index 00000000000..fcabcac89f7
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.trunc( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.trunc(float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check b/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check
new file mode 100644
index 00000000000..f9c93b3def5
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check
diff --git a/llvm/test/CodeGen/R600/llvm.AMDIL.fabs..ll b/llvm/test/CodeGen/R600/llvm.AMDIL.fabs..ll
new file mode 100644
index 00000000000..11430369e4c
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDIL.fabs..ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDIL.fabs.( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDIL.fabs.(float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check b/llvm/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check
new file mode 100644
index 00000000000..ff3124ca903
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check
diff --git a/llvm/test/CodeGen/R600/llvm.AMDIL.max..ll b/llvm/test/CodeGen/R600/llvm.AMDIL.max..ll
new file mode 100644
index 00000000000..337371234ae
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDIL.max..ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = call float @llvm.AMDIL.max.( float %r0, float %r1)
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDIL.max.(float ,float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDIL.max..ll.check b/llvm/test/CodeGen/R600/llvm.AMDIL.max..ll.check
new file mode 100644
index 00000000000..9ae4070fdc8
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDIL.max..ll.check
diff --git a/llvm/test/CodeGen/R600/llvm.AMDIL.min..ll b/llvm/test/CodeGen/R600/llvm.AMDIL.min..ll
new file mode 100644
index 00000000000..76a87188808
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDIL.min..ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = call float @llvm.AMDIL.min.( float %r0, float %r1)
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDIL.min.(float ,float ) readnone
diff --git a/llvm/test/CodeGen/R600/llvm.AMDIL.min..ll.check b/llvm/test/CodeGen/R600/llvm.AMDIL.min..ll.check
new file mode 100644
index 00000000000..3d343bdea61
--- /dev/null
+++ b/llvm/test/CodeGen/R600/llvm.AMDIL.min..ll.check