[Power9] Fix the resource list for the COPY instruction.

The COPY instruction was listed as a 4 cycle instruction.
It is now listed correctly as a 2 cycle ALU instruction.

llvm-svn: 328647

2 files changed, 112 insertions, 156 deletions

diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
index 4eb2c39fa29..0b7181e5a67 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -2542,14 +2542,14 @@ body:             |
     %6 = LI8 889
     %7,%17 = LWZUX %0, killed %6 :: (load 4 from %ir.arrayidx, !tbaa !8)
     ; CHECK: LWZU 889, %0
-    ; CHECK-LATE: lwzu 5, 889(4)
+    ; CHECK-LATE: lwzu {{[0-9]+}}, 889({{[0-9]+}})
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -2
     %12,%18 = LWZUX %0, killed %11 :: (load 4 from %ir.arrayidx3, !tbaa !8)
     ; CHECK: LWZU -2, %0
-    ; CHECK-LATE: lwzu 4, -2(3)
+    ; CHECK-LATE: lwzu {{[0-9]+}}, -2({{[0-9]+}})
     %13 = ADD4 killed %12, killed %7
     %15 = IMPLICIT_DEF
     %14 = INSERT_SUBREG %15, killed %13, 1
@@ -2772,14 +2772,14 @@ body:             |
     %6 = LI8 100
     %7,%14 = LDUX %0, killed %6 :: (load 8 from %ir.arrayidx, !tbaa !10)
     ; CHECK: LDU 100, %0
-    ; CHECK-LATE: ldu 5, 100(4)
+    ; CHECK-LATE: ldu {{[0-9]+}}, 100({{[0-9]+}})
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 200
     %12,%15 = LDUX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !10)
     ; CHECK: LDU 200, %0
-    ; CHECK-LATE: ldu 4, 200(3)
+    ; CHECK-LATE: ldu {{[0-9]+}}, 200({{[0-9]+}})
     %13 = ADD8 killed %12, killed %7
     $x3 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -2920,14 +2920,14 @@ body:             |
     %6 = LI8 440
     %7,%14 = LFDUX %0, killed %6 :: (load 8 from %ir.arrayidx, !tbaa !12)
     ; CHECK: LFDU 440, %0
-    ; CHECK-LATE: lfdu 0, 440(4)
+    ; CHECK-LATE: lfdu {{[0-9]+}}, 440({{[0-9]+}})
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 16
     %12,%15 = LFDUX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !12)
     ; CHECK: LFDU 16, %0
-    ; CHECK-LATE: lfdu 1, 16(3)
+    ; CHECK-LATE: lfdu {{[0-9]+}}, 16({{[0-9]+}})
     %13 = FADD killed %7, killed %12, implicit $rm
     $f1 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $f1
@@ -2993,14 +2993,14 @@ body:             |
     %6 = RLDIC %4, 3, 29
     %7 = LFDX %0, killed %6 :: (load 8 from %ir.arrayidx, !tbaa !12)
     ; CHECK: LFD -20, killed %6
-    ; CHECK-LATE: lfd 0, -20(5)
+    ; CHECK-LATE: lfd {{[0-9]+}}, -20({{[0-9]+}})
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = RLDIC %9, 3, 29
     %12 = LFDX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !12)
     ; CHECK: LFD -20, killed %11
-    ; CHECK-LATE: lfd 1, -20(4)
+    ; CHECK-LATE: lfd {{[0-9]+}}, -20({{[0-9]+}})
     %13 = FADD killed %7, killed %12, implicit $rm
     $f1 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $f1
@@ -5100,14 +5100,14 @@ body:             |
     %8 = LI8 966
     %13 = STBUX %3, %0, killed %8 :: (store 1 into %ir.arrayidx, !tbaa !3)
     ; CHECK: STBU %3, 966, %0
-    ; CHECK-LATE: 4, 966(5)
+    ; CHECK-LATE: {{[0-9]+}}, 966({{[0-9]+}})
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = LI8 777
     %14 = STBUX %3, %0, killed %12 :: (store 1 into %ir.arrayidx3, !tbaa !3)
     ; CHECK: STBU %3, 777, %0
-    ; CHECK-LATE: 4, 777(3)
+    ; CHECK-LATE: {{[0-9]+}}, 777({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -5248,14 +5248,14 @@ body:             |
     %8 = LI8 32000
     %13 = STHUX %3, %0, killed %8 :: (store 2 into %ir.arrayidx, !tbaa !6)
     ; CHECK: STHU %3, 32000, %0
-    ; CHECK-LATE: sthu 4, 32000(5)
+    ; CHECK-LATE: sthu {{[0-9]+}}, 32000({{[0-9]+}})
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = LI8 -761
     %14 = STHUX %3, %0, killed %12 :: (store 2 into %ir.arrayidx3, !tbaa !6)
     ; CHECK: STHU %3, -761, %0
-    ; CHECK-LATE: sthu 4, -761(3)
+    ; CHECK-LATE: sthu {{[0-9]+}}, -761({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -5321,14 +5321,14 @@ body:             |
     %8 = LI8 900
     STHX %3, %0, killed %8 :: (store 1 into %ir.arrayidx, !tbaa !3)
     ; CHECK: STH %3, 900, %0
-    ; CHECK-LATE: sth 4, 900(3)
+    ; CHECK-LATE: sth {{[0-9]+}}, 900({{[0-9]+}})
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = LI8 -900
     STHX %3, %0, killed %12 :: (store 1 into %ir.arrayidx3, !tbaa !3)
     ; CHECK: STH %3, -900, %0
-    ; CHECK-LATE: sth 4, -900(3)
+    ; CHECK-LATE: sth {{[0-9]+}}, -900({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -5396,14 +5396,14 @@ body:             |
     %8 = LI8 111
     %13 = STWUX %3, %0, killed %8 :: (store 4 into %ir.arrayidx, !tbaa !8)
     ; CHECK: STWU %3, 111, %0
-    ; CHECK-LATE: stwu 4, 111(5)
+    ; CHECK-LATE: stwu {{[0-9]+}}, 111({{[0-9]+}})
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = LI8 0
     %14 = STWUX %3, %0, killed %12 :: (store 4 into %ir.arrayidx3, !tbaa !8)
     ; CHECK: STWU %3, 0, %0
-    ; CHECK-LATE: stwu 4, 0(3)
+    ; CHECK-LATE: stwu {{[0-9]+}}, 0({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -5542,14 +5542,14 @@ body:             |
     %7 = LI8 444
     %12 = STDUX %1, %0, killed %7 :: (store 8 into %ir.arrayidx, !tbaa !10)
     ; CHECK: STDU %1, 444, %0
-    ; CHECK-LATE: stdu 4, 444(5)
+    ; CHECK-LATE: stdu {{[0-9]+}}, 444({{[0-9]+}})
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -8
     %13 = STDUX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !10)
     ; CHECK: STDU %1, -8, %0
-    ; CHECK-LATE: stdu 4, -8(3)
+    ; CHECK-LATE: stdu {{[0-9]+}}, -8({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -5613,14 +5613,14 @@ body:             |
     %7 = LI8 900
     STDX %1, %0, killed %7 :: (store 8 into %ir.arrayidx, !tbaa !10)
     ; CHECK: STD %1, 1000, killed %7
-    ; CHECK-LATE: 4, 1000(5)
+    ; CHECK-LATE: {{[0-9]+}}, 1000({{[0-9]+}})
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -900
     STDX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !10)
     ; CHECK: STD %1, 1000, killed %11
-    ; CHECK-LATE: 4, 1000(6)
+    ; CHECK-LATE: {{[0-9]+}}, 1000({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -5757,14 +5757,14 @@ body:             |
     %7 = LI8 111
     %12 = STFSUX %1, %0, killed %7 :: (store 4 into %ir.arrayidx, !tbaa !14)
     ; CHECK: STFSU %1, 111, %0
-    ; CHECK-LATE: stfsu 1, 111(4)
+    ; CHECK-LATE: stfsu {{[0-9]+}}, 111({{[0-9]+}})
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 987
     %13 = STFSUX %1, %0, killed %11 :: (store 4 into %ir.arrayidx3, !tbaa !14)
     ; CHECK: STFSU %1, 987, %0
-    ; CHECK-LATE: stfsu 1, 987(3)
+    ; CHECK-LATE: stfsu {{[0-9]+}}, 987({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -5901,14 +5901,14 @@ body:             |
     %7 = LI8 -9038
     %12 = STFDUX %1, %0, killed %7 :: (store 8 into %ir.arrayidx, !tbaa !12)
     ; CHECK: STFDU %1, -9038, %0
-    ; CHECK-LATE: stfdu 1, -9038(4)
+    ; CHECK-LATE: stfdu {{[0-9]+}}, -9038({{[0-9]+}})
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 6477
     %13 = STFDUX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !12)
     ; CHECK: STFDU %1, 6477, %0
-    ; CHECK-LATE: stfdu 1, 6477(3)
+    ; CHECK-LATE: stfdu {{[0-9]+}}, 6477({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
diff --git a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
index c8c7d797c00..9e70d244162 100644
--- a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
+++ b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
@@ -106,13 +106,11 @@ entry:
 define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_halfword_8_1
-; CHECK: vsldoi 2, 2, 2, 6
-; CHECK: vinserth 3, 2, 14
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 6
+; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 14
 ; CHECK-BE-LABEL: shuffle_vector_halfword_8_1
-; CHECK-BE: vsldoi 2, 2, 2, 12
-; CHECK-BE: vinserth 3, 2, 0
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 12
+; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 0
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
@@ -122,13 +120,11 @@ entry:
 define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_halfword_9_7
-; CHECK: vsldoi 2, 2, 2, 10
-; CHECK: vinserth 3, 2, 12
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 10
+; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 12
 ; CHECK-BE-LABEL: shuffle_vector_halfword_9_7
-; CHECK-BE: vsldoi 2, 2, 2, 8
-; CHECK-BE: vinserth 3, 2, 2
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 8
+; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 2
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
@@ -139,9 +135,8 @@ entry:
 ; CHECK: vinserth 3, 2, 10
 ; CHECK: vmr 2, 3
 ; CHECK-BE-LABEL: shuffle_vector_halfword_10_4
-; CHECK-BE: vsldoi 2, 2, 2, 2
-; CHECK-BE: vinserth 3, 2, 4
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 2
+; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 4
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
@@ -149,13 +144,11 @@ entry:
 define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_halfword_11_2
-; CHECK: vsldoi 2, 2, 2, 4
-; CHECK: vinserth 3, 2, 8
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 4
+; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 8
 ; CHECK-BE-LABEL: shuffle_vector_halfword_11_2
-; CHECK-BE: vsldoi 2, 2, 2, 14
-; CHECK-BE: vinserth 3, 2, 6
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 14
+; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 6
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
@@ -163,13 +156,11 @@ entry:
 define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_halfword_12_6
-; CHECK: vsldoi 2, 2, 2, 12
-; CHECK: vinserth 3, 2, 6
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 12
+; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 6
 ; CHECK-BE-LABEL: shuffle_vector_halfword_12_6
-; CHECK-BE: vsldoi 2, 2, 2, 6
-; CHECK-BE: vinserth 3, 2, 8
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 6
+; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 8
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15>
   ret <8 x i16> %vecins
 }
@@ -177,9 +168,8 @@ entry:
 define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_halfword_13_3
-; CHECK: vsldoi 2, 2, 2, 2
-; CHECK: vinserth 3, 2, 4
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 2
+; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 4
 ; CHECK-BE-LABEL: shuffle_vector_halfword_13_3
 ; CHECK-BE: vinserth 3, 2, 10
 ; CHECK-BE: vmr 2, 3
@@ -190,13 +180,11 @@ entry:
 define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_halfword_14_5
-; CHECK: vsldoi 2, 2, 2, 14
-; CHECK: vinserth 3, 2, 2
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 14
+; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 2
 ; CHECK-BE-LABEL: shuffle_vector_halfword_14_5
-; CHECK-BE: vsldoi 2, 2, 2, 4
-; CHECK-BE: vinserth 3, 2, 12
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 4
+; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 12
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15>
   ret <8 x i16> %vecins
 }
@@ -204,13 +192,11 @@ entry:
 define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_halfword_15_0
-; CHECK: vsldoi 2, 2, 2, 8
-; CHECK: vinserth 3, 2, 0
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 8
+; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 0
 ; CHECK-BE-LABEL: shuffle_vector_halfword_15_0
-; CHECK-BE: vsldoi 2, 2, 2, 10
-; CHECK-BE: vinserth 3, 2, 14
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 10
+; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 14
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
   ret <8 x i16> %vecins
 }
@@ -498,9 +484,8 @@ entry:
 ; CHECK: vinsertb 3, 2, 15
 ; CHECK: vmr 2, 3
 ; CHECK-BE-LABEL: shuffle_vector_byte_16_8
-; CHECK-BE: vsldoi 2, 2, 2, 1
-; CHECK-BE: vinsertb 3, 2, 0
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 1
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 0
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -508,13 +493,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_17_1
-; CHECK: vsldoi 2, 2, 2, 7
-; CHECK: vinsertb 3, 2, 14
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 7
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 14
 ; CHECK-BE-LABEL: shuffle_vector_byte_17_1
-; CHECK-BE: vsldoi 2, 2, 2, 10
-; CHECK-BE: vinsertb 3, 2, 1
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 10
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 1
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -522,13 +505,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_18_10
-; CHECK: vsldoi 2, 2, 2, 14
-; CHECK: vinsertb 3, 2, 13
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 14
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 13
 ; CHECK-BE-LABEL: shuffle_vector_byte_18_10
-; CHECK-BE: vsldoi 2, 2, 2, 3
-; CHECK-BE: vinsertb 3, 2, 2
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 3
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 2
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -536,13 +517,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_19_3
-; CHECK: vsldoi 2, 2, 2, 5
-; CHECK: vinsertb 3, 2, 12
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 5
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 12
 ; CHECK-BE-LABEL: shuffle_vector_byte_19_3
-; CHECK-BE: vsldoi 2, 2, 2, 12
-; CHECK-BE: vinsertb 3, 2, 3
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 12
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 3
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -550,13 +529,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_20_12
-; CHECK: vsldoi 2, 2, 2, 12
-; CHECK: vinsertb 3, 2, 11
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 12
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 11
 ; CHECK-BE-LABEL: shuffle_vector_byte_20_12
-; CHECK-BE: vsldoi 2, 2, 2, 5
-; CHECK-BE: vinsertb 3, 2, 4
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 5
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 4
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -564,13 +541,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_21_5
-; CHECK: vsldoi 2, 2, 2, 3
-; CHECK: vinsertb 3, 2, 10
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 3
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 10
 ; CHECK-BE-LABEL: shuffle_vector_byte_21_5
-; CHECK-BE: vsldoi 2, 2, 2, 14
-; CHECK-BE: vinsertb 3, 2, 5
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 14
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 5
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -578,13 +553,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_22_14
-; CHECK: vsldoi 2, 2, 2, 10
-; CHECK: vinsertb 3, 2, 9
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 10
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 9
 ; CHECK-BE-LABEL: shuffle_vector_byte_22_14
-; CHECK-BE: vsldoi 2, 2, 2, 7
-; CHECK-BE: vinsertb 3, 2, 6
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 7
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 6
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -592,9 +565,8 @@ entry:
 define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_23_7
-; CHECK: vsldoi 2, 2, 2, 1
-; CHECK: vinsertb 3, 2, 8
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 1
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 8
 ; CHECK-BE-LABEL: shuffle_vector_byte_23_7
 ; CHECK-BE: vinsertb 3, 2, 7
 ; CHECK-BE: vmr 2, 3
@@ -605,13 +577,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_24_0
-; CHECK: vsldoi 2, 2, 2, 8
-; CHECK: vinsertb 3, 2, 7
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 8
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 7
 ; CHECK-BE-LABEL: shuffle_vector_byte_24_0
-; CHECK-BE: vsldoi 2, 2, 2, 9
-; CHECK-BE: vinsertb 3, 2, 8
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 9
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 8
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -619,13 +589,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_25_9
-; CHECK: vsldoi 2, 2, 2, 15
-; CHECK: vinsertb 3, 2, 6
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 15
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 6
 ; CHECK-BE-LABEL: shuffle_vector_byte_25_9
-; CHECK-BE: vsldoi 2, 2, 2, 2
-; CHECK-BE: vinsertb 3, 2, 9
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 2
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 9
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -633,13 +601,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_26_2
-; CHECK: vsldoi 2, 2, 2, 6
-; CHECK: vinsertb 3, 2, 5
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 6
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 5
 ; CHECK-BE-LABEL: shuffle_vector_byte_26_2
-; CHECK-BE: vsldoi 2, 2, 2, 11
-; CHECK-BE: vinsertb 3, 2, 10
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 11
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 10
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -647,13 +613,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_27_11
-; CHECK: vsldoi 2, 2, 2, 13
-; CHECK: vinsertb 3, 2, 4
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 13
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 4
 ; CHECK-BE-LABEL: shuffle_vector_byte_27_11
-; CHECK-BE: vsldoi 2, 2, 2, 4
-; CHECK-BE: vinsertb 3, 2, 11
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 4
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 11
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -661,13 +625,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_28_4
-; CHECK: vsldoi 2, 2, 2, 4
-; CHECK: vinsertb 3, 2, 3
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 4
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 3
 ; CHECK-BE-LABEL: shuffle_vector_byte_28_4
-; CHECK-BE: vsldoi 2, 2, 2, 13
-; CHECK-BE: vinsertb 3, 2, 12
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 13
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 12
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -675,13 +637,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_29_13
-; CHECK: vsldoi 2, 2, 2, 11
-; CHECK: vinsertb 3, 2, 2
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 11
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 2
 ; CHECK-BE-LABEL: shuffle_vector_byte_29_13
-; CHECK-BE: vsldoi 2, 2, 2, 6
-; CHECK-BE: vinsertb 3, 2, 13
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 6
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 13
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31>
   ret <16 x i8> %vecins
 }
@@ -689,13 +649,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_30_6
-; CHECK: vsldoi 2, 2, 2, 2
-; CHECK: vinsertb 3, 2, 1
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 2
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 1
 ; CHECK-BE-LABEL: shuffle_vector_byte_30_6
-; CHECK-BE: vsldoi 2, 2, 2, 15
-; CHECK-BE: vinsertb 3, 2, 14
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 15
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 14
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31>
   ret <16 x i8> %vecins
 }
@@ -703,13 +661,11 @@ entry:
 define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) {
 entry:
 ; CHECK-LABEL: shuffle_vector_byte_31_15
-; CHECK: vsldoi 2, 2, 2, 9
-; CHECK: vinsertb 3, 2, 0
-; CHECK: vmr 2, 3
+; CHECK: vsldoi {{[0-9]+}}, 2, 2, 9
+; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 0
 ; CHECK-BE-LABEL: shuffle_vector_byte_31_15
-; CHECK-BE: vsldoi 2, 2, 2, 8
-; CHECK-BE: vinsertb 3, 2, 15
-; CHECK-BE: vmr 2, 3
+; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 8
+; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 15
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15>
   ret <16 x i8> %vecins
 }