Implemented Support of IA interrupt and exception handlers:

http://lists.llvm.org/pipermail/cfe-dev/2015-September/045171.html

Differential Revision: http://reviews.llvm.org/D15567

llvm-svn: 256155

2 files changed, 165 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/X86/x86-32-intrcc.ll b/llvm/test/CodeGen/X86/x86-32-intrcc.ll
new file mode 100644
index 00000000000..908da3d1120
--- /dev/null
+++ b/llvm/test/CodeGen/X86/x86-32-intrcc.ll
@@ -0,0 +1,79 @@
+; RUN: llc -mtriple=i686-unknown-unknown < %s | FileCheck %s

+; RUN: llc -mtriple=i686-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0

+

+%struct.interrupt_frame = type { i32, i32, i32, i32, i32 }

+

+@llvm.used = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i32)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i32)* @test_isr_clobbers to i8*)], section "llvm.metadata"

+

+; Spills eax, putting original esp at +4.

+; No stack adjustment if declared with no error code

+define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {

+  ; CHECK-LABEL: test_isr_no_ecode:

+  ; CHECK: pushl %eax

+  ; CHECK: movl 12(%esp), %eax

+  ; CHECK: popl %eax

+  ; CHECK: iretl

+  ; CHECK0-LABEL: test_isr_no_ecode:

+  ; CHECK0: pushl %eax

+  ; CHECK0: leal 4(%esp), %eax

+  ; CHECK0: movl 8(%eax), %eax

+  ; CHECK0: popl %eax

+  ; CHECK0: iretl

+  %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2

+  %flags = load i32, i32* %pflags, align 4

+  call void asm sideeffect "", "r"(i32 %flags)

+  ret void

+}

+

+; Spills eax and ecx, putting original esp at +8. Stack is adjusted up another 4 bytes

+; before return, popping the error code.

+define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i32 %ecode) {

+  ; CHECK-LABEL: test_isr_ecode

+  ; CHECK: pushl %ecx

+  ; CHECK: pushl %eax

+  ; CHECK: movl 8(%esp), %eax

+  ; CHECK: movl 20(%esp), %ecx

+  ; CHECK: popl %eax

+  ; CHECK: popl %ecx

+  ; CHECK: addl $4, %esp

+  ; CHECK: iretl

+  ; CHECK0-LABEL: test_isr_ecode

+  ; CHECK0: pushl %ecx

+  ; CHECK0: pushl %eax

+  ; CHECK0: movl 8(%esp), %eax

+  ; CHECK0: leal 12(%esp), %ecx

+  ; CHECK0: movl 8(%ecx), %ecx

+  ; CHECK0: popl %eax

+  ; CHECK0: popl %ecx

+  ; CHECK0: addl $4, %esp

+  ; CHECK0: iretl

+  %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2

+  %flags = load i32, i32* %pflags, align 4

+  call x86_fastcallcc void asm sideeffect "", "r,r"(i32 %flags, i32 %ecode)

+  ret void

+}

+

+; All clobbered registers must be saved

+define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i32 %ecode) {

+  call void asm sideeffect "", "~{eax},~{ebx},~{ebp}"()

+  ; CHECK-LABEL: test_isr_clobbers

+  ; CHECK-SSE-NEXT: pushl %ebp

+  ; CHECK-SSE-NEXT: pushl %ebx

+  ; CHECK-SSE-NEXT; pushl %eax

+  ; CHECK-SSE-NEXT: popl %eax

+  ; CHECK-SSE-NEXT: popl %ebx

+  ; CHECK-SSE-NEXT: popl %ebp

+  ; CHECK-SSE-NEXT: addl $4, %esp

+  ; CHECK-SSE-NEXT: iretl

+  ; CHECK0-LABEL: test_isr_clobbers

+  ; CHECK0-SSE-NEXT: pushl %ebp

+  ; CHECK0-SSE-NEXT: pushl %ebx

+  ; CHECK0-SSE-NEXT; pushl %eax

+  ; CHECK0-SSE-NEXT: popl %eax

+  ; CHECK0-SSE-NEXT: popl %ebx

+  ; CHECK0-SSE-NEXT: popl %ebp

+  ; CHECK0-SSE-NEXT: addl $4, %esp

+  ; CHECK0-SSE-NEXT: iretl

+  ret void

+}

+

diff --git a/llvm/test/CodeGen/X86/x86-64-intrcc.ll b/llvm/test/CodeGen/X86/x86-64-intrcc.ll
new file mode 100644
index 00000000000..8f70b391fa1
--- /dev/null
+++ b/llvm/test/CodeGen/X86/x86-64-intrcc.ll
@@ -0,0 +1,86 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s

+; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0

+

+%struct.interrupt_frame = type { i64, i64, i64, i64, i64 }

+

+@llvm.used = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_clobbers to i8*)], section "llvm.metadata"

+

+; Spills rax, putting original esp at +8.

+; No stack adjustment if declared with no error code

+define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {

+  ; CHECK-LABEL: test_isr_no_ecode:

+  ; CHECK: pushq %rax

+  ; CHECK: movq 24(%rsp), %rax

+  ; CHECK: popq %rax

+  ; CHECK: iretq

+  ; CHECK0-LABEL: test_isr_no_ecode:

+  ; CHECK0: pushq %rax

+  ; CHECK0: leaq 8(%rsp), %rax

+  ; CHECK0: movq 16(%rax), %rax

+  ; CHECK0: popq %rax

+  ; CHECK0: iretq

+  %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2

+  %flags = load i64, i64* %pflags, align 4

+  call void asm sideeffect "", "r"(i64 %flags)

+  ret void

+}

+

+; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes

+; before return, popping the error code.

+define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i64 %ecode) {

+  ; CHECK-LABEL: test_isr_ecode

+  ; CHECK: pushq %rax

+  ; CHECK: pushq %rcx

+  ; CHECK: movq 16(%rsp), %rax

+  ; CHECK: movq 40(%rsp), %rcx

+  ; CHECK: popq %rcx

+  ; CHECK: popq %rax

+  ; CHECK: addq $8, %rsp

+  ; CHECK: iretq

+  ; CHECK0-LABEL: test_isr_ecode

+  ; CHECK0: pushq %rax

+  ; CHECK0: pushq %rcx

+  ; CHECK0: movq 16(%rsp), %rax

+  ; CHECK0: leaq 24(%rsp), %rcx

+  ; CHECK0: movq 16(%rcx), %rcx

+  ; CHECK0: popq %rcx

+  ; CHECK0: popq %rax

+  ; CHECK0: addq $8, %rsp

+  ; CHECK0: iretq

+  %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2

+  %flags = load i64, i64* %pflags, align 4

+  call void asm sideeffect "", "r,r"(i64 %flags, i64 %ecode)

+  ret void

+}

+

+; All clobbered registers must be saved

+define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) {

+  call void asm sideeffect "", "~{rax},~{rbx},~{rbp},~{r11},~{xmm0}"()

+  ; CHECK-LABEL: test_isr_clobbers

+  ; CHECK-SSE-NEXT: pushq %rax

+  ; CHECK-SSE-NEXT; pushq %r11

+  ; CHECK-SSE-NEXT: pushq %rbp

+  ; CHECK-SSE-NEXT: pushq %rbx

+  ; CHECK-SSE-NEXT: movaps %xmm0

+  ; CHECK-SSE-NEXT: movaps %xmm0

+  ; CHECK-SSE-NEXT: popq %rbx

+  ; CHECK-SSE-NEXT: popq %rbp

+  ; CHECK-SSE-NEXT: popq %r11

+  ; CHECK-SSE-NEXT: popq %rax

+  ; CHECK-SSE-NEXT: addq $8, %rsp

+  ; CHECK-SSE-NEXT: iretq

+  ; CHECK0-LABEL: test_isr_clobbers

+  ; CHECK0-SSE-NEXT: pushq %rax

+  ; CHECK0-SSE-NEXT; pushq %r11

+  ; CHECK0-SSE-NEXT: pushq %rbp

+  ; CHECK0-SSE-NEXT: pushq %rbx

+  ; CHECK0-SSE-NEXT: movaps %xmm0

+  ; CHECK0-SSE-NEXT: movaps %xmm0

+  ; CHECK0-SSE-NEXT: popq %rbx

+  ; CHECK0-SSE-NEXT: popq %rbp

+  ; CHECK0-SSE-NEXT: popq %r11

+  ; CHECK0-SSE-NEXT: popq %rax

+  ; CHECK0-SSE-NEXT: addq $8, %rsp

+  ; CHECK0-SSE-NEXT: iretq

+  ret void

+}
\ No newline at end of file