[mips] Correct the definitions of the unaligned word memory operation instructions

These instructions lacked the correct predicates, were not marked
as loads and stores and lacked the proper instruction mapping information.

In the case of microMIPS sw(l|r)e (EVA) these instructions were using the load
EVA description.

Reviewers: abeserminji, smaksimovic, atanasyan

Differential Revision: https://reviews.llvm.org/D45626

llvm-svn: 330326

2 files changed, 159 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
new file mode 100644
index 00000000000..438a7e1d0e4
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
@@ -0,0 +1,124 @@
+# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \
+# RUN:     -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
+
+# Test that MIPS unaligned load/store instructions can be mapped to their
+# corresponding microMIPS instructions.
+--- |
+  define void @g(i32* %a, i32* %b) {
+  entry:
+    %0 = load i32, i32* %a, align 1
+    store i32 %0, i32* %b, align 1
+    ret void
+  }
+
+  define void @g2(i32* %a, i32* %b) {
+  entry:
+    %0 = load i32, i32* %a, align 1
+    store i32 %0, i32* %b, align 1
+    ret void
+  }
+...
+---
+name:            g
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+liveins:
+  - { reg: '$a0', virtual-reg: '%0' }
+  - { reg: '$a1', virtual-reg: '%1' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.0.entry:
+    liveins: $a0, $a1
+
+    %1:gpr32 = COPY $a1
+    %0:gpr32 = COPY $a0
+    %3:gpr32 = IMPLICIT_DEF
+    %2:gpr32 = LWL %0, 0, %3 :: (load 4 from %ir.a, align 1)
+    %4:gpr32 = LWR %0, 3, %2 :: (load 4 from %ir.a, align 1)
+    SWL %4, %1, 0 :: (store 4 into %ir.b, align 1)
+    SWR %4, %1, 3 :: (store 4 into %ir.b, align 1)
+    RetRA
+
+...
+---
+name:            g2
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+liveins:
+  - { reg: '$a0', virtual-reg: '%0' }
+  - { reg: '$a1', virtual-reg: '%1' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.0.entry:
+    liveins: $a0, $a1
+
+    %1:gpr32 = COPY $a1
+    %0:gpr32 = COPY $a0
+    %3:gpr32 = IMPLICIT_DEF
+    %2:gpr32 = LWLE %0, 0, %3 :: (load 4 from %ir.a, align 1)
+    %4:gpr32 = LWRE %0, 3, %2 :: (load 4 from %ir.a, align 1)
+    SWLE %4, %1, 0 :: (store 4 into %ir.b, align 1)
+    SWRE %4, %1, 3 :: (store 4 into %ir.b, align 1)
+    RetRA
+
+...
+
+# CHECK-LABEL: g:
+# CHECK:  0: 60 24 00 00   lwl $1, 0($4)
+# CHECK:  4: 60 24 10 03   lwr $1, 3($4)
+# CHECK:  8: 60 25 80 00   swl $1, 0($5)
+# CHECK:  c: 60 25 90 03   swr $1, 3($5)
+
+# CHECK-LABEL: g2:
+# CHECK: 14: 60 24 64 00   lwle  $1, 0($4)
+# CHECK: 18: 60 24 66 03   lwre  $1, 3($4)
+# CHECK: 1c: 60 25 a0 00   swle  $1, 0($5)
+# CHECK: 20: 60 25 a2 03   swre  $1, 3($5)
diff --git a/llvm/test/CodeGen/Mips/unaligned-memops.ll b/llvm/test/CodeGen/Mips/unaligned-memops.ll
new file mode 100644
index 00000000000..af290a7bcf0
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/unaligned-memops.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MIPS
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MICROMIPS
+
+; Test that the correct ISA version of the unaligned memory operations is
+; selected up front.
+
+define void @g2(i32* %a, i32* %b) {
+  ; MIPS-LABEL: name: g2
+  ; MIPS: bb.0.entry:
+  ; MIPS:   liveins: $a0, $a1
+  ; MIPS:   [[COPY:%[0-9]+]]:gpr32 = COPY $a1
+  ; MIPS:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
+  ; MIPS:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+  ; MIPS:   [[LWL:%[0-9]+]]:gpr32 = LWL [[COPY1]], 0, [[DEF]] :: (load 4 from %ir.a, align 1)
+  ; MIPS:   [[LWR:%[0-9]+]]:gpr32 = LWR [[COPY1]], 3, [[LWL]] :: (load 4 from %ir.a, align 1)
+  ; MIPS:   SWL [[LWR]], [[COPY]], 0 :: (store 4 into %ir.b, align 1)
+  ; MIPS:   SWR [[LWR]], [[COPY]], 3 :: (store 4 into %ir.b, align 1)
+  ; MIPS:   RetRA
+  ; MICROMIPS-LABEL: name: g2
+  ; MICROMIPS: bb.0.entry:
+  ; MICROMIPS:   liveins: $a0, $a1
+  ; MICROMIPS:   [[COPY:%[0-9]+]]:gpr32 = COPY $a1
+  ; MICROMIPS:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
+  ; MICROMIPS:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+  ; MICROMIPS:   [[LWL_MM:%[0-9]+]]:gpr32 = LWL_MM [[COPY1]], 0, [[DEF]] :: (load 4 from %ir.a, align 1)
+  ; MICROMIPS:   [[LWR_MM:%[0-9]+]]:gpr32 = LWR_MM [[COPY1]], 3, [[LWL_MM]] :: (load 4 from %ir.a, align 1)
+  ; MICROMIPS:   SWL_MM [[LWR_MM]], [[COPY]], 0 :: (store 4 into %ir.b, align 1)
+  ; MICROMIPS:   SWR_MM [[LWR_MM]], [[COPY]], 3 :: (store 4 into %ir.b, align 1)
+  ; MICROMIPS:   RetRA
+entry:
+  %0 = load i32, i32* %a, align 1
+  store i32 %0, i32* %b, align 1
+  ret void
+}