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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-24 11:02:38 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-24 11:02:38 +0000 |
| commit | 5b9d591ad108653cb4d696da2bda023ddbb51501 (patch) | |
| tree | e595bc347ca8f088071e3fc249893ecc2400caa1 /llvm/test | |
| parent | d20e91edad13091ad69544780ab863d45cfaca48 (diff) | |
| download | bcm5719-llvm-5b9d591ad108653cb4d696da2bda023ddbb51501.tar.gz bcm5719-llvm-5b9d591ad108653cb4d696da2bda023ddbb51501.zip | |
[PowerPC] Support bd(n)zl and bd(n)zlrl
This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.
llvm-svn: 184720
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/PowerPC/ppc64-encoding-ext.s | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s index 31525c77719..9ca8199de9d 100644 --- a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s @@ -54,9 +54,12 @@ # FIXME: bdnza target # CHECK: bdnzlr # encoding: [0x4e,0x00,0x00,0x20] bdnzlr -# FIXME: bdnzl target +# CHECK: bdnzl target # encoding: [0x42,0x00,A,0bAAAAAA01] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnzl target # FIXME: bdnzla target -# FIXME: bdnzlrl +# CHECK: bdnzlrl # encoding: [0x4e,0x00,0x00,0x21] + bdnzlrl # FIXME: bdnzt 2, target # FIXME: bdnzt target @@ -89,9 +92,12 @@ # FIXME: bdza target # CHECK: bdzlr # encoding: [0x4e,0x40,0x00,0x20] bdzlr -# FIXME: bdzl target +# CHECK: bdzl target # encoding: [0x42,0x40,A,0bAAAAAA01] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdzl target # FIXME: bdzla target -# FIXME: bdzlrl +# CHECK: bdzlrl # encoding: [0x4e,0x40,0x00,0x21] + bdzlrl # FIXME: bdzt 2, target # FIXME: bdzt target |
