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authorAnton Korobeynikov <asl@math.spbu.ru>2009-10-10 22:17:47 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-10-10 22:17:47 +0000
commit5b8826b4da55896226a5b24e1039f08865e3e580 (patch)
tree1f749643805c2c656cc0ce8b245f47db9eb7fd00 /llvm/test
parentd4f70053ae3345d40d405d4d437188a2c9d7647c (diff)
downloadbcm5719-llvm-5b8826b4da55896226a5b24e1039f08865e3e580.tar.gz
bcm5719-llvm-5b8826b4da55896226a5b24e1039f08865e3e580.zip
It seems that OR operation does not affect status reg at all.
Remove impdef of SRW. This fixes PR4779 llvm-svn: 83739
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll14
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll b/llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
new file mode 100644
index 00000000000..856eb9db3f6
--- /dev/null
+++ b/llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=msp430 < %s
+; PR4779
+define void @foo() nounwind {
+entry:
+ %r = alloca i8 ; <i8*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ volatile load i8* %r, align 1 ; <i8>:0 [#uses=1]
+ or i8 %0, 1 ; <i8>:1 [#uses=1]
+ volatile store i8 %1, i8* %r, align 1
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
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