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authorAleksandar Beserminji <Aleksandar.Beserminji@imgtec.com>2017-09-29 09:32:14 +0000
committerAleksandar Beserminji <Aleksandar.Beserminji@imgtec.com>2017-09-29 09:32:14 +0000
commit502dcb035a2c5f70ff0f1436be26bc8ad27d86eb (patch)
tree745903f1ca2b6a945779a73252895bbeb8807539 /llvm/test
parent97c327a6ccf1db3c59fe3c263213da84a2b03401 (diff)
downloadbcm5719-llvm-502dcb035a2c5f70ff0f1436be26bc8ad27d86eb.tar.gz
bcm5719-llvm-502dcb035a2c5f70ff0f1436be26bc8ad27d86eb.zip
[mips] Reordering callseq* nodes to be linear
Fix nested callseq* nodes by moving callseq_start after the arguments calculation to temporary registers, so that callseq* nodes in resulting DAG are linear. Differential Revision: https://reviews.llvm.org/D37328 llvm-svn: 314497
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/Mips/callseq_order.ll55
-rw-r--r--llvm/test/CodeGen/Mips/largeimmprinting.ll11
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/mul.ll2
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll2
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/srem.ll2
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/udiv.ll2
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/urem.ll2
7 files changed, 66 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/Mips/callseq_order.ll b/llvm/test/CodeGen/Mips/callseq_order.ll
new file mode 100644
index 00000000000..0da511ac714
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/callseq_order.ll
@@ -0,0 +1,55 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -o /dev/null \
+; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
+; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=mips64el-linux-gnu -o /dev/null \
+; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
+; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=mips-linux-gnu -o /dev/null \
+; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
+; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=mips64-linux-gnu -o /dev/null \
+; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
+; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
+
+
+%struct.Str1 = type { [64 x i32] }
+
+@s1 = common global %struct.Str1 zeroinitializer, align 4
+
+define void @foo1() {
+entry:
+ call void @bar1(%struct.Str1* byval align 4 @s1)
+ ret void
+ ; CHECK-LABEL: *** MachineFunction at end of ISel ***
+ ; CHECK-LABEL: # Machine code for function foo1: IsSSA, TracksLiveness
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <es:memcpy>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <ga:@bar1>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK-LABEL: # End machine code for function foo1.
+}
+
+declare void @bar1(%struct.Str1* byval align 4)
+
+define void @foo2() {
+entry:
+ call void @bar2(%struct.Str1* byval align 4 @s1, %struct.Str1* byval align 4 @s1)
+ ret void
+ ; CHECK-LABEL: *** MachineFunction at end of ISel ***
+ ; CHECK-LABEL: # Machine code for function foo2: IsSSA, TracksLiveness
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <es:memcpy>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <es:memcpy>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK: ADJCALLSTACKDOWN
+ ; CHECK: JAL <ga:@bar2>
+ ; CHECK: ADJCALLSTACKUP
+ ; CHECK-LABEL: # End machine code for function foo2.
+}
+
+declare void @bar2(%struct.Str1* byval align 4, %struct.Str1* byval align 4)
+
diff --git a/llvm/test/CodeGen/Mips/largeimmprinting.ll b/llvm/test/CodeGen/Mips/largeimmprinting.ll
index f27e11425b9..2225fc78e52 100644
--- a/llvm/test/CodeGen/Mips/largeimmprinting.ll
+++ b/llvm/test/CodeGen/Mips/largeimmprinting.ll
@@ -1,8 +1,9 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \
-; RUN: FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \
-; RUN: FileCheck %s -check-prefix=64
+; RUN: llc -march=mipsel -relocation-model=pic -verify-machineinstrs < %s | \
+; RUN: FileCheck %s -check-prefix=32
+; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic \
+; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
+; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64
%struct.S1 = type { [65536 x i8] }
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
index 1562372ce9a..e32aa646c04 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -268,7 +268,7 @@ entry:
; MM64R6: daddu $2, $[[T1]], $[[T0]]
; MM64R6-DAG: dmul $3, $5, $7
- ; MM32: lw $25, %call16(__multi3)($16)
+ ; MM32: lw $25, %call16(__multi3)
%r = mul i128 %a, %b
ret i128 %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
index defd25bb41a..087b28b3acd 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
@@ -190,7 +190,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
; 64R6: ld $25, %call16(__divti3)($gp)
- ; MM32: lw $25, %call16(__divti3)($16)
+ ; MM32: lw $25, %call16(__divti3)
; MM64: ld $25, %call16(__divti3)($2)
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll
index 42664d7457e..7466e5679bb 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll
@@ -182,7 +182,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
; 64R6: ld $25, %call16(__modti3)($gp)
- ; MM32: lw $25, %call16(__modti3)($16)
+ ; MM32: lw $25, %call16(__modti3)
; MM64: ld $25, %call16(__modti3)($2)
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
index 78ab36442a9..122d1385353 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
@@ -152,7 +152,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
; 64-R6: ld $25, %call16(__udivti3)($gp)
- ; MM32: lw $25, %call16(__udivti3)($16)
+ ; MM32: lw $25, %call16(__udivti3)
; MM64: ld $25, %call16(__udivti3)($2)
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll
index 160c126c7e3..7fd3d79f843 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll
@@ -208,7 +208,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
; 64R6: ld $25, %call16(__umodti3)($gp)
- ; MM32: lw $25, %call16(__umodti3)($16)
+ ; MM32: lw $25, %call16(__umodti3)
; MM64: ld $25, %call16(__umodti3)($2)
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