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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-22 19:30:38 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-22 19:30:38 +0000 |
| commit | 4d2ea3c69683b97cacaaafc3156a33827de5f66d (patch) | |
| tree | dfb8d4c7fc9c3f7f9891ef4e72190f6db456aa42 /llvm/test | |
| parent | 0d6b347fa526052b97aa0e945762f80acddde087 (diff) | |
| download | bcm5719-llvm-4d2ea3c69683b97cacaaafc3156a33827de5f66d.tar.gz bcm5719-llvm-4d2ea3c69683b97cacaaafc3156a33827de5f66d.zip | |
[mips] Fix MipsAsmParser::parseCCRRegs.
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format.
llvm-svn: 186861
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/Mips/mips-fpu-instructions.s | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/test/MC/Mips/mips-fpu-instructions.s b/llvm/test/MC/Mips/mips-fpu-instructions.s index 5ff31f3e493..256ce4513b7 100644 --- a/llvm/test/MC/Mips/mips-fpu-instructions.s +++ b/llvm/test/MC/Mips/mips-fpu-instructions.s @@ -138,7 +138,8 @@ # FP move instructions #------------------------------------------------------------------------------ -# CHECK: cfc1 $6, $fcc0 # encoding: [0x00,0x00,0x46,0x44] +# CHECK: cfc1 $6, $0 # encoding: [0x00,0x00,0x46,0x44] +# CHECK: ctc1 $10, $31 # encoding: [0x00,0xf8,0xca,0x44] # CHECK: mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44] # CHECK: mfhi $5 # encoding: [0x10,0x28,0x00,0x00] # CHECK: mflo $5 # encoding: [0x12,0x28,0x00,0x00] @@ -162,6 +163,7 @@ # CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c] cfc1 $a2,$0 + ctc1 $10,$31 mfc1 $a2,$f7 mfhi $a1 mflo $a1 |
