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| author | Mikael Holmen <mikael.holmen@ericsson.com> | 2019-12-06 08:03:13 +0100 |
|---|---|---|
| committer | Mikael Holmen <mikael.holmen@ericsson.com> | 2019-12-10 11:22:35 +0100 |
| commit | 4d280d3ac06aae0453859c83e025de8610596495 (patch) | |
| tree | 965a89a39c01528cf5524b710feda155ecb3da93 /llvm/test | |
| parent | dac5ddb482361cde11ac43e94c43acc94a3b78aa (diff) | |
| download | bcm5719-llvm-4d280d3ac06aae0453859c83e025de8610596495.tar.gz bcm5719-llvm-4d280d3ac06aae0453859c83e025de8610596495.zip | |
Add testcases exposing PR44135
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/legalize-bitcast.ll | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/legalize-bitcast.ll b/llvm/test/CodeGen/ARM/legalize-bitcast.ll new file mode 100644 index 00000000000..a5d72aa1993 --- /dev/null +++ b/llvm/test/CodeGen/ARM/legalize-bitcast.ll @@ -0,0 +1,56 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O0 -mtriple=armebv7 -target-abi apcs -o - %s | FileCheck %s + +@vec6_p = external global <6 x i16> + +define i32 @vec_to_int() { +; CHECK-LABEL: vec_to_int: +; CHECK: @ %bb.0: @ %bb.0 +; CHECK-NEXT: push {r4} +; CHECK-NEXT: sub sp, sp, #28 +; CHECK-NEXT: movw r0, :lower16:vec6_p +; CHECK-NEXT: movt r0, :upper16:vec6_p +; CHECK-NEXT: vld1.8 {d16}, [r0]! +; CHECK-NEXT: ldr r0, [r0] +; CHECK-NEXT: @ implicit-def: $d17 +; CHECK-NEXT: vmov.32 d17[0], r0 +; CHECK-NEXT: vrev32.16 d17, d17 +; CHECK-NEXT: vrev16.8 d16, d16 +; CHECK-NEXT: vmov.f64 d18, d16 +; CHECK-NEXT: vmov.f64 d19, d17 +; CHECK-NEXT: vstmia sp, {d18, d19} @ 16-byte Spill +; CHECK-NEXT: b .LBB0_1 +; CHECK-NEXT: .LBB0_1: @ %bb.1 +; CHECK-NEXT: vldmia sp, {d16, d17} @ 16-byte Reload +; CHECK-NEXT: vrev32.16 q9, q8 +; CHECK-NEXT: @ kill: def $d19 killed $d19 killed $q9 +; CHECK-NEXT: vmov.32 r0, d19[1] +; CHECK-NEXT: add sp, sp, #28 +; CHECK-NEXT: pop {r4} +; CHECK-NEXT: bx lr +bb.0: + %vec6 = load <6 x i16>, <6 x i16>* @vec6_p, align 1 + br label %bb.1 + +bb.1: + %0 = bitcast <6 x i16> %vec6 to i96 + %1 = trunc i96 %0 to i32 + ret i32 %1 +} + +define i16 @int_to_vec(i80 %in) { +; CHECK-LABEL: int_to_vec: +; CHECK: @ %bb.0: +; CHECK-NEXT: sub sp, sp, #4 +; CHECK-NEXT: vmov.i32 q8, #0x0 +; CHECK-NEXT: vrev32.16 q8, q8 +; CHECK-NEXT: @ kill: def $d16 killed $d16 killed $q8 +; CHECK-NEXT: vmov.u16 r3, d16[0] +; CHECK-NEXT: str r0, [sp] @ 4-byte Spill +; CHECK-NEXT: mov r0, r3 +; CHECK-NEXT: add sp, sp, #4 +; CHECK-NEXT: bx lr + %vec = bitcast i80 %in to <5 x i16> + %e0 = extractelement <5 x i16> %vec, i32 0 + ret i16 %e0 +} |
