tests: tweak MIR for ARM tests to correct MI issues

The Machine Instruction Verifier flagged some issues in the serialized MIR.
Adjust the input to correct them.

Fixes the remaining portion of PR27480.

llvm-svn: 267578

2 files changed, 7 insertions, 5 deletions

diff --git a/llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir b/llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir
index b5c4c47f9e3..a5da48d0e81 100644
--- a/llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir
+++ b/llvm/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir
@@ -1,4 +1,4 @@
-# RUN: llc -start-after machine-cp -stop-after=if-converter -mtriple=thumbv7 %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: llc -mtriple thumbv7 -verify-machineinstrs -start-after machine-cp -stop-after if-converter %s -o /dev/null 2>&1 | FileCheck %s
 --- |
   ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll'
   target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
@@ -86,6 +86,7 @@ tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%r0' }
+  - { reg: '%r1' }
   - { reg: '%r2' }
   - { reg: '%r3' }
 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
@@ -122,7 +123,7 @@ stack:
 body:             |
   bb.0.entry:
     successors: %bb.1, %bb.2.if.end
-    liveins: %r0, %r2, %r3, %lr, %r7
+    liveins: %r0, %r1, %r2, %r3, %lr, %r7
 
     DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
@@ -151,11 +152,11 @@ body:             |
     DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
     DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
     %r1 = COPY killed %r2, debug-location !32
+    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     %r2 = COPY killed %r3, debug-location !32
     tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
     %r0 = t2MOVi 0, 14, _, _
     %sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     tBX_RET 14, _, implicit %r0, debug-location !34
 # Verify that the DBG_VALUE is ignored.
 # CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0
diff --git a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
index ae7a6350170..eb4a44b7e17 100644
--- a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
+++ b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple thumbv7 -start-after if-converter -print-before=post-RA-sched -print-after=post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s
+# RUN: llc -mtriple thumbv7 -verify-machineinstrs -start-after if-converter -print-before post-RA-sched -print-after post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s
 --- |
   ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll'
   target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
@@ -97,6 +97,7 @@ tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%r0' }
+  - { reg: '%r1' }
   - { reg: '%r2' }
   - { reg: '%r3' }
 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
@@ -132,7 +133,7 @@ stack:
   - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
 body:             |
   bb.0.entry:
-    liveins: %r0, %r2, %r3, %lr, %r7
+    liveins: %r0, %r1, %r2, %r3, %lr, %r7
 
     DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28