summaryrefslogtreecommitdiffstats
path: root/llvm/test
diff options
context:
space:
mode:
authorThomas Lively <tlively@google.com>2018-10-05 00:45:20 +0000
committerThomas Lively <tlively@google.com>2018-10-05 00:45:20 +0000
commit4b47d08e527b322dac729f0a4fea2eed48d8cf56 (patch)
tree83e165afe9901755568c5bf56070b21267c02058 /llvm/test
parent19a3c7e19f9b5e8a9fe3ed8a078180e30c05591e (diff)
downloadbcm5719-llvm-4b47d08e527b322dac729f0a4fea2eed48d8cf56.tar.gz
bcm5719-llvm-4b47d08e527b322dac729f0a4fea2eed48d8cf56.zip
[WebAssembly] Saturating arithmetic intrinsics
Summary: Depends on D52805. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52813 llvm-svn: 343833
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/WebAssembly/simd-arith.ll8
-rw-r--r--llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll104
-rw-r--r--llvm/test/MC/WebAssembly/simd-encodings.s24
3 files changed, 132 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
index 317b87fd692..9b496226598 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
@@ -1,9 +1,9 @@
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM,SIMD128-VM-SLOW
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM,SIMD128-VM-FAST
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128,NO-SIMD128-SLOW
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128,NO-SIMD128-FAST
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
; Test that basic SIMD128 arithmetic operations assemble as expected.
diff --git a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
index 1c693164305..f9f4eb0cf9e 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -11,6 +11,58 @@ target triple = "wasm32-unknown-unknown"
; ==============================================================================
; 16 x i8
; ==============================================================================
+; CHECK-LABEL: add_sat_s_v16i8:
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.add.saturate.signed.v16i8(<16 x i8>, <16 x i8>)
+define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
+ %a = call <16 x i8> @llvm.wasm.add.saturate.signed.v16i8(
+ <16 x i8> %x, <16 x i8> %y
+ )
+ ret <16 x i8> %a
+}
+
+; CHECK-LABEL: add_sat_u_v16i8:
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.add.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>)
+define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
+ %a = call <16 x i8> @llvm.wasm.add.saturate.unsigned.v16i8(
+ <16 x i8> %x, <16 x i8> %y
+ )
+ ret <16 x i8> %a
+}
+
+; CHECK-LABEL: sub_sat_s_v16i8:
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(<16 x i8>, <16 x i8>)
+define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
+ %a = call <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(
+ <16 x i8> %x, <16 x i8> %y
+ )
+ ret <16 x i8> %a
+}
+
+; CHECK-LABEL: sub_sat_u_v16i8:
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>)
+define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
+ %a = call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(
+ <16 x i8> %x, <16 x i8> %y
+ )
+ ret <16 x i8> %a
+}
+
; CHECK-LABEL: any_v16i8:
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result i32{{$}}
@@ -49,6 +101,58 @@ define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
; ==============================================================================
; 8 x i16
; ==============================================================================
+; CHECK-LABEL: add_sat_s_v8i16:
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.add.saturate.signed.v8i16(<8 x i16>, <8 x i16>)
+define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
+ %a = call <8 x i16> @llvm.wasm.add.saturate.signed.v8i16(
+ <8 x i16> %x, <8 x i16> %y
+ )
+ ret <8 x i16> %a
+}
+
+; CHECK-LABEL: add_sat_u_v8i16:
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.add.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>)
+define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
+ %a = call <8 x i16> @llvm.wasm.add.saturate.unsigned.v8i16(
+ <8 x i16> %x, <8 x i16> %y
+ )
+ ret <8 x i16> %a
+}
+
+; CHECK-LABEL: sub_sat_s_v8i16:
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(<8 x i16>, <8 x i16>)
+define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
+ %a = call <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(
+ <8 x i16> %x, <8 x i16> %y
+ )
+ ret <8 x i16> %a
+}
+
+; CHECK-LABEL: sub_sat_u_v8i16:
+; SIMD128-NEXT: .param v128, v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>)
+define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
+ %a = call <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(
+ <8 x i16> %x, <8 x i16> %y
+ )
+ ret <8 x i16> %a
+}
+
; CHECK-LABEL: any_v8i16:
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result i32{{$}}
diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s
index a8c9b6df445..02d07674c16 100644
--- a/llvm/test/MC/WebAssembly/simd-encodings.s
+++ b/llvm/test/MC/WebAssembly/simd-encodings.s
@@ -145,6 +145,30 @@
# CHECK: i64x2.neg # encoding: [0xfd,0x27]
i64x2.neg
+ # CHECK: i8x16.add_saturate_s # encoding: [0xfd,0x28]
+ i8x16.add_saturate_s
+
+ # CHECK: i8x16.add_saturate_u # encoding: [0xfd,0x29]
+ i8x16.add_saturate_u
+
+ # CHECK: i16x8.add_saturate_s # encoding: [0xfd,0x2a]
+ i16x8.add_saturate_s
+
+ # CHECK: i16x8.add_saturate_u # encoding: [0xfd,0x2b]
+ i16x8.add_saturate_u
+
+ # CHECK: i8x16.sub_saturate_s # encoding: [0xfd,0x2c]
+ i8x16.sub_saturate_s
+
+ # CHECK: i8x16.sub_saturate_u # encoding: [0xfd,0x2d]
+ i8x16.sub_saturate_u
+
+ # CHECK: i16x8.sub_saturate_s # encoding: [0xfd,0x2e]
+ i16x8.sub_saturate_s
+
+ # CHECK: i16x8.sub_saturate_u # encoding: [0xfd,0x2f]
+ i16x8.sub_saturate_u
+
# CHECK: i8x16.shl # encoding: [0xfd,0x30]
i8x16.shl
OpenPOWER on IntegriCloud