[ARM] Add v8.1a "Rounding Double Multiply Add/Subtract" extension

Reviewers: t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8503

llvm-svn: 233301

6 files changed, 629 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/ARM/neon-v8.1a.ll b/llvm/test/CodeGen/ARM/neon-v8.1a.ll
new file mode 100644
index 00000000000..91259139d44
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/neon-v8.1a.ll
@@ -0,0 +1,166 @@
+; RUN: llc < %s -mtriple=armv8 -mattr=+v8.1a | FileCheck %s
+
+;-----------------------------------------------------------------------------
+; RDMA Vector
+
+declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
+
+declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>)
+
+declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i16> @test_vqrdmlah_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) {
+; CHECK-LABEL: test_vqrdmlah_v4i16:
+   %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs,  <4 x i16> %rhs)
+   %retval =  call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %acc,  <4 x i16> %prod)
+; CHECK: vqrdmlah.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+   ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_vqrdmlah_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) {
+; CHECK-LABEL: test_vqrdmlah_v8i16:
+   %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
+   %retval =  call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK: vqrdmlah.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
+   ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_vqrdmlah_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) {
+; CHECK-LABEL: test_vqrdmlah_v2i32:
+   %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
+   %retval =  call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK: vqrdmlah.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+   ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_vqrdmlah_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) {
+; CHECK-LABEL: test_vqrdmlah_v4i32:
+   %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
+   %retval =  call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK: vqrdmlah.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
+   ret <4 x i32> %retval
+}
+
+define <4 x i16> @test_vqrdmlsh_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) {
+; CHECK-LABEL: test_vqrdmlsh_v4i16:
+   %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs,  <4 x i16> %rhs)
+   %retval =  call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %acc, <4 x i16> %prod)
+; CHECK: vqrdmlsh.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+   ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_vqrdmlsh_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) {
+; CHECK-LABEL: test_vqrdmlsh_v8i16:
+   %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
+   %retval =  call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK: vqrdmlsh.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
+   ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_vqrdmlsh_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) {
+; CHECK-LABEL: test_vqrdmlsh_v2i32:
+   %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
+   %retval =  call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK: vqrdmlsh.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+   ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_vqrdmlsh_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) {
+; CHECK-LABEL: test_vqrdmlsh_v4i32:
+   %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
+   %retval =  call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK: vqrdmlsh.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
+   ret <4 x i32> %retval
+}
+
+;-----------------------------------------------------------------------------
+; RDMA Scalar
+
+define <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_vqrdmlah_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)
+  %retval =  call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %acc, <4 x i16> %prod)
+; CHECK: vqrdmlah.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[3]
+  ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_vqrdmlahq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_vqrdmlahq_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+  %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)
+  %retval =  call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK: vqrdmlah.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[2]
+  ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_vqrdmlah_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
+  %prod = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)
+  %retval =  call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK: vqrdmlah.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[1]
+  ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_vqrdmlahq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_vqrdmlahq_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <4 x i32> zeroinitializer
+  %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
+  %retval =  call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK: vqrdmlah.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[0]
+  ret <4 x i32> %retval
+}
+
+define <4 x i16> @test_vqrdmlsh_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_vqrdmlsh_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)
+  %retval =  call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %acc, <4 x i16> %prod)
+; CHECK: vqrdmlsh.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[3]
+  ret <4 x i16> %retval
+}
+
+define <8 x i16> @test_vqrdmlshq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <4 x i16> %v) {
+; CHECK-LABEL: test_vqrdmlshq_lane_s16:
+entry:
+  %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+  %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle)
+  %retval =  call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %acc, <8 x i16> %prod)
+; CHECK: vqrdmlsh.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[2]
+  ret <8 x i16> %retval
+}
+
+define <2 x i32> @test_vqrdmlsh_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_vqrdmlsh_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
+  %prod = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle)
+  %retval =  call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %acc, <2 x i32> %prod)
+; CHECK: vqrdmlsh.s32  {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[1]
+  ret <2 x i32> %retval
+}
+
+define <4 x i32> @test_vqrdmlshq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <2 x i32> %v) {
+; CHECK-LABEL: test_vqrdmlshq_lane_s32:
+entry:
+  %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <4 x i32> zeroinitializer
+  %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
+  %retval =  call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %acc, <4 x i32> %prod)
+; CHECK: vqrdmlsh.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[0]
+  ret <4 x i32> %retval
+}
diff --git a/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s b/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s
new file mode 100644
index 00000000000..261e628f2ba
--- /dev/null
+++ b/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s
@@ -0,0 +1,174 @@
+//RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aTHUMB
+//RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s
+//RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aARM
+//RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s
+
+//RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>1 |& FileCheck %s --check-prefix=CHECK-V8
+//RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>1 |& FileCheck %s --check-prefix=CHECK-V8
+
+
+  .text
+//CHECK-V8THUMB: .text
+
+  vqrdmlah.i8   q0, q1, q2
+  vqrdmlah.u16  d0, d1, d2
+  vqrdmlsh.f32  q3, q4, q5
+  vqrdmlsh.f64  d3, d5, d5
+
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlah.i8   q0, q1, q2
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlah.u16  d0, d1, d2
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlsh.f32  q3, q4, q5
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlsh.f64  d3, d5, d5
+//CHECK-ERROR:           ^
+//CHECK-V8: error: invalid operand for instruction
+//CHECK-V8:   vqrdmlah.i8   q0, q1, q2
+//CHECK-V8:           ^
+//CHECK-V8: error: invalid operand for instruction
+//CHECK-V8:   vqrdmlah.u16  d0, d1, d2
+//CHECK-V8:           ^
+//CHECK-V8: error: invalid operand for instruction
+//CHECK-V8:   vqrdmlsh.f32  q3, q4, q5
+//CHECK-V8:           ^
+//CHECK-V8: error: invalid operand for instruction
+//CHECK-V8   vqrdmlsh.f64  d3, d5, d5
+//CHECK-V8:           ^
+
+  vqrdmlah.s16    d0, d1, d2
+//CHECK-V81aARM:   vqrdmlah.s16  d0, d1, d2      @ encoding: [0x12,0x0b,0x11,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s16  d0, d1, d2      @ encoding: [0x11,0xff,0x12,0x0b]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlah.s16    d0, d1, d2
+//CHECK-V8:  ^
+
+  vqrdmlah.s32  d0, d1, d2
+//CHECK-V81aARM:   vqrdmlah.s32  d0, d1, d2      @ encoding: [0x12,0x0b,0x21,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s32  d0, d1, d2      @ encoding: [0x21,0xff,0x12,0x0b]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlah.s32  d0, d1, d2
+//CHECK-V8:  ^
+
+  vqrdmlah.s16  q0, q1, q2
+//CHECK-V81aARM:   vqrdmlah.s16  q0, q1, q2      @ encoding: [0x54,0x0b,0x12,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s16  q0, q1, q2      @ encoding: [0x12,0xff,0x54,0x0b]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlah.s16  q0, q1, q2
+//CHECK-V8:  ^
+
+  vqrdmlah.s32  q2, q3, q0
+//CHECK-V81aARM:   vqrdmlah.s32  q2, q3, q0      @ encoding: [0x50,0x4b,0x26,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s32  q2, q3, q0      @ encoding: [0x26,0xff,0x50,0x4b]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlah.s32  q2, q3, q0
+//CHECK-V8:  ^
+
+
+  vqrdmlsh.s16  d7, d6, d5
+//CHECK-V81aARM:   vqrdmlsh.s16  d7, d6, d5      @ encoding: [0x15,0x7c,0x16,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s16  d7, d6, d5      @ encoding: [0x16,0xff,0x15,0x7c]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlsh.s16  d7, d6, d5
+//CHECK-V8:  ^
+
+  vqrdmlsh.s32  d0, d1, d2
+//CHECK-V81aARM:   vqrdmlsh.s32  d0, d1, d2      @ encoding: [0x12,0x0c,0x21,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s32  d0, d1, d2      @ encoding: [0x21,0xff,0x12,0x0c]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlsh.s32  d0, d1, d2
+//CHECK-V8:  ^
+
+  vqrdmlsh.s16  q0, q1, q2
+//CHECK-V81aARM:   vqrdmlsh.s16  q0, q1, q2      @ encoding: [0x54,0x0c,0x12,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s16  q0, q1, q2      @ encoding: [0x12,0xff,0x54,0x0c]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlsh.s16  q0, q1, q2
+//CHECK-V8:  ^
+
+  vqrdmlsh.s32    q3, q4, q5
+//CHECK-V81aARM:   vqrdmlsh.s32  q3, q4, q5      @ encoding: [0x5a,0x6c,0x28,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s32  q3, q4, q5      @ encoding: [0x28,0xff,0x5a,0x6c]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlsh.s32  q3, q4, q5
+//CHECK-V8:  ^
+
+
+  vqrdmlah.i8   q0, q1, d9[7]
+  vqrdmlah.u16  d0, d1, d2[3]
+  vqrdmlsh.f32  q3, q4, d5[1]
+  vqrdmlsh.f64  d3, d5, d5[0]
+
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlah.i8   q0, q1, d9[7]
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlah.u16  d0, d1, d2[3]
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlsh.f32  q3, q4, d5[1]
+//CHECK-ERROR:           ^
+//CHECK-ERROR: error: invalid operand for instruction
+//CHECK-ERROR:   vqrdmlsh.f64  d3, d5, d5[0]
+//CHECK-ERROR:           ^
+
+  vqrdmlah.s16  d0, d1, d2[0]
+//CHECK-V81aARM:   vqrdmlah.s16 d0, d1, d2[0]    @ encoding: [0x42,0x0e,0x91,0xf2]
+//CHECK-V81aTHUMB: vqrdmlah.s16  d0, d1, d2[0]   @ encoding: [0x91,0xef,0x42,0x0e]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlah.s16  d0, d1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlah.s32  d0, d1, d2[0]
+//CHECK-V81aARM:   vqrdmlah.s32 d0, d1, d2[0]    @ encoding: [0x42,0x0e,0xa1,0xf2]
+//CHECK-V81aTHUMB: vqrdmlah.s32  d0, d1, d2[0]   @ encoding: [0xa1,0xef,0x42,0x0e]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlah.s32  d0, d1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlah.s16  q0, q1, d2[0]
+//CHECK-V81aARM:   vqrdmlah.s16  q0, q1, d2[0]   @ encoding: [0x42,0x0e,0x92,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s16  q0, q1, d2[0]   @ encoding: [0x92,0xff,0x42,0x0e]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlah.s16  q0, q1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlah.s32  q0, q1, d2[0]
+//CHECK-V81aARM:   vqrdmlah.s32  q0, q1, d2[0]   @ encoding: [0x42,0x0e,0xa2,0xf3]
+//CHECK-V81aTHUMB: vqrdmlah.s32  q0, q1, d2[0]   @ encoding: [0xa2,0xff,0x42,0x0e]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlah.s32  q0, q1, d2[0]
+//CHECK-V8:  ^
+
+
+  vqrdmlsh.s16  d0, d1, d2[0]
+//CHECK-V81aARM:   vqrdmlsh.s16 d0, d1, d2[0]    @ encoding: [0x42,0x0f,0x91,0xf2]
+//CHECK-V81aTHUMB: vqrdmlsh.s16  d0, d1, d2[0]   @ encoding: [0x91,0xef,0x42,0x0f]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlsh.s16  d0, d1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlsh.s32  d0, d1, d2[0]
+//CHECK-V81aARM:   vqrdmlsh.s32 d0, d1, d2[0]    @ encoding: [0x42,0x0f,0xa1,0xf2]
+//CHECK-V81aTHUMB: vqrdmlsh.s32  d0, d1, d2[0]   @ encoding: [0xa1,0xef,0x42,0x0f]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlsh.s32  d0, d1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlsh.s16  q0, q1, d2[0]
+//CHECK-V81aARM:   vqrdmlsh.s16 q0, q1, d2[0]    @ encoding: [0x42,0x0f,0x92,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s16  q0, q1, d2[0]   @ encoding: [0x92,0xff,0x42,0x0f]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlsh.s16  q0, q1, d2[0]
+//CHECK-V8:  ^
+
+  vqrdmlsh.s32  q0, q1, d2[0]
+//CHECK-V81aARM:   vqrdmlsh.s32 q0, q1, d2[0]    @ encoding: [0x42,0x0f,0xa2,0xf3]
+//CHECK-V81aTHUMB: vqrdmlsh.s32  q0, q1, d2[0]   @ encoding: [0xa2,0xff,0x42,0x0f]
+//CHECK-V8: error: instruction requires: v8.1a
+//CHECK-V8:  vqrdmlsh.s32  q0, q1, d2[0]
+//CHECK-V8:  ^
diff --git a/llvm/test/MC/Disassembler/ARM/armv8.1a.txt b/llvm/test/MC/Disassembler/ARM/armv8.1a.txt
new file mode 100644
index 00000000000..de0c89ee790
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/armv8.1a.txt
@@ -0,0 +1,36 @@
+# RUN: llvm-mc -triple armv8 -mattr=+v8.1a  --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a
+# RUN: not llvm-mc -triple armv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
+
+[0x54,0x0b,0x12,0xf3]
+[0x12,0x0b,0x21,0xf3]
+[0x54,0x0c,0x12,0xf3]
+[0x12,0x0c,0x21,0xf3]
+# CHECK-V81a:  vqrdmlah.s16  q0, q1, q2
+# CHECK-V81a:  vqrdmlah.s32  d0, d1, d2
+# CHECK-V81a:  vqrdmlsh.s16  q0, q1, q2
+# CHECK-V81a:  vqrdmlsh.s32  d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x54,0x0b,0x12,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0x0b,0x21,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x54,0x0c,0x12,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0x0c,0x21,0xf3]
+
+[0x42,0x0e,0x92,0xf3]
+[0x42,0x0e,0xa1,0xf2]
+[0x42,0x0f,0x92,0xf3]
+[0x42,0x0f,0xa1,0xf2]
+# CHECK-V81a:  vqrdmlah.s16 q0, q1, d2[0]
+# CHECK-V81a:  vqrdmlah.s32 d0, d1, d2[0]
+# CHECK-V81a:  vqrdmlsh.s16 q0, q1, d2[0]
+# CHECK-V81a:  vqrdmlsh.s32 d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0e,0x92,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0e,0xa1,0xf2]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0f,0x92,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0f,0xa1,0xf2]
diff --git a/llvm/test/MC/Disassembler/ARM/invalid-armv8.1a.txt b/llvm/test/MC/Disassembler/ARM/invalid-armv8.1a.txt
new file mode 100644
index 00000000000..1a9f2754fc9
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/invalid-armv8.1a.txt
@@ -0,0 +1,83 @@
+# RUN: not llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s
+
+# Check, if sizes 00 and 11 are undefined for RDMA
+[0x12,0x0b,0x01,0xf3] # vqrdmlah.s8   d0, d1, d2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x12,0x0b,0x01,0xf3] # vqrdmlah.s8   d0, d1, d2
+# CHECK-NEXT:  ^
+
+[0x12,0x0b,0x31,0xf3] # vqrdmlah.s64  d0, d1, d2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x12,0x0b,0x31,0xf3] # vqrdmlah.s64  d0, d1, d2
+# CHECK-NEXT:  ^
+
+[0x54,0x0b,0x02,0xf3] # vqrdmlah.s8   q0, q1, q2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0b,0x02,0xf3] # vqrdmlah.s8   q0, q1, q2
+# CHECK-NEXT:  ^
+
+[0x54,0x0b,0x32,0xf3] # vqrdmlah.s64  q2, q3, q0
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0b,0x32,0xf3] # vqrdmlah.s64  q2, q3, q0
+# CHECK-NEXT:  ^
+
+[0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8   d0, d1, d2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8   d0, d1, d2
+# CHECK-NEXT:  ^
+
+[0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64  d0, d1, d2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64  d0, d1, d2
+# CHECK-NEXT:  ^
+
+[0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8   q0, q1, q2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8   q0, q1, q2
+# CHECK-NEXT:  ^
+
+[0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64  q0, q1, q2
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64  q0, q1, q2
+# CHECK-NEXT:  ^
+
+[0x42,0x0e,0x81,0xf2] # vqrdmlah.s8   d0, d1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0x81,0xf2] # vqrdmlah.s8   d0, d1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64  d0, d1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64  d0, d1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0e,0x82,0xf3] # vqrdmlah.s8   q0, q1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0x82,0xf3] # vqrdmlah.s8   q0, q1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64  q0, q1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64  q0, q1, d2[0]
+# CHECK-NEXT:  ^
+
+
+[0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8   d0, d1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8   d0, d1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64  d0, d1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64  d0, d1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8   q0, q1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8   q0, q1, d2[0]
+# CHECK-NEXT:  ^
+
+[0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64  q0, q1, d2[0]
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64  q0, q1, d2[0]
+# CHECK-NEXT:  ^
diff --git a/llvm/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt b/llvm/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt
new file mode 100644
index 00000000000..555b8c3c54d
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt
@@ -0,0 +1,72 @@
+# RUN: not llvm-mc -triple thumbv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s
+
+# Check, if sizes 00 and 11 are undefined for RDMA
+[0x01,0xff,0x12,0x0b] # vqrdmlah.s8   d0, d1, d2
+[0x31,0xff,0x12,0x0b] # vqrdmlah.s64  d0, d1, d2
+[0x02,0xff,0x54,0x0b] # vqrdmlah.s8   q0, q1, q2
+[0x06,0xff,0x50,0x4b] # vqrdmlah.s64  q2, q3, q0
+
+[0x01,0xff,0x12,0x0c] # vqrdmlsh.s8   d0, d1, d2
+[0x31,0xff,0x12,0x0c] # vqrdmlsh.s64  d0, d1, d2
+[0x02,0xff,0x54,0x0c] # vqrdmlsh.s8   q0, q1, q2
+[0x32,0xff,0x54,0x0c] # vqrdmlsh.s64  q0, q1, q2
+
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x01,0xff,0x12,0x0b] # vqrdmlah.s8   d0, d1, d2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x31,0xff,0x12,0x0b] # vqrdmlah.s64  d0, d1, d2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x02,0xff,0x54,0x0b] # vqrdmlah.s8   q0, q1, q2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x06,0xff,0x50,0x4b] # vqrdmlah.s64  q2, q3, q0
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x01,0xff,0x12,0x0c] # vqrdmlsh.s8   d0, d1, d2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x31,0xff,0x12,0x0c] # vqrdmlsh.s64  d0, d1, d2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x02,0xff,0x54,0x0c] # vqrdmlsh.s8   q0, q1, q2
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x32,0xff,0x54,0x0c] # vqrdmlsh.s64  q0, q1, q2
+# CHECK-NEXT:  ^
+
+[0x81,0xef,0x42,0x0e] # vqrdmlah.s8   d0, d1, d2[0]
+[0xb1,0xef,0x42,0x0e] # vqrdmlah.s64  d0, d1, d2[0]
+[0x82,0xff,0x42,0x0e] # vqrdmlah.s8   q0, q1, d2[0]
+[0xb2,0xff,0x42,0x0e] # vqrdmlah.s64  q0, q1, d2[0]
+
+[0x81,0xef,0x42,0x0f] # vqrdmlsh.s8   d0, d1, d2[0]
+[0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64  d0, d1, d2[0]
+[0x82,0xff,0x42,0x0f] # vqrdmlsh.s8   q0, q1, d2[0]
+[0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64  q0, q1, d2[0]
+
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x81,0xef,0x42,0x0e] # vqrdmlah.s8   d0, d1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0xb1,0xef,0x42,0x0e] # vqrdmlah.s64  d0, d1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x82,0xff,0x42,0x0e] # vqrdmlah.s8   q0, q1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0xb2,0xff,0x42,0x0e] # vqrdmlah.s64  q0, q1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x81,0xef,0x42,0x0f] # vqrdmlsh.s8   d0, d1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64  d0, d1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0x82,0xff,0x42,0x0f] # vqrdmlsh.s8   q0, q1, d2[0]
+# CHECK-NEXT:  ^
+# CHECK:      warning: invalid instruction encoding
+# CHECK-NEXT: [0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64  q0, q1, d2[0]
+# CHECK-NEXT:  ^
diff --git a/llvm/test/MC/Disassembler/ARM/thumb-v8.1a.txt b/llvm/test/MC/Disassembler/ARM/thumb-v8.1a.txt
new file mode 100644
index 00000000000..bb0f1dca1a1
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/thumb-v8.1a.txt
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple thumbv8 -mattr=+v8.1a  --disassemble < %s |& FileCheck %s --check-prefix=CHECK-V81a
+# RUN: not llvm-mc -triple thumbv8 -mattr=+v8 --disassemble < %s |& FileCheck %s --check-prefix=CHECK-V8
+
+[0x11,0xff,0x12,0x0b]
+# CHECK-V81a: vqrdmlah.s16  d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x11,0xff,0x12,0x0b]
+# CHECK-V8: ^
+
+[0x21,0xff,0x12,0x0b]
+# CHECK-V81a: vqrdmlah.s32  d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x21,0xff,0x12,0x0b]
+# CHECK-V8: ^
+
+[0x12,0xff,0x54,0x0b]
+# CHECK-V81a: vqrdmlah.s16  q0, q1, q2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0xff,0x54,0x0b]
+# CHECK-V8: ^
+
+[0x26,0xff,0x50,0x4b]
+# CHECK-V81a: vqrdmlah.s32  q2, q3, q0
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x26,0xff,0x50,0x4b]
+# CHECK-V8: ^
+
+[0x16,0xff,0x15,0x7c]
+# CHECK-V81a: vqrdmlsh.s16  d7, d6, d5
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x16,0xff,0x15,0x7c]
+# CHECK-V8: ^
+
+[0x21,0xff,0x12,0x0c]
+# CHECK-V81a: vqrdmlsh.s32  d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x21,0xff,0x12,0x0c]
+# CHECK-V8: ^
+
+[0x12,0xff,0x54,0x0c]
+# CHECK-V81a: vqrdmlsh.s16  q0, q1, q2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0xff,0x54,0x0c]
+# CHECK-V8: ^
+
+[0x28,0xff,0x5a,0x6c]
+# CHECK-V81a: vqrdmlsh.s32  q3, q4, q5
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x28,0xff,0x5a,0x6c]
+# CHECK-V8: ^
+
+[0x91,0xef,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s16  d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x91,0xef,0x42,0x0e]
+# CHECK-V8: ^
+
+[0xa1,0xef,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s32  d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa1,0xef,0x42,0x0e]
+# CHECK-V8: ^
+
+[0x92,0xff,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s16  q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x92,0xff,0x42,0x0e]
+# CHECK-V8: ^
+
+[0xa2,0xff,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s32  q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa2,0xff,0x42,0x0e]
+# CHECK-V8: ^
+
+[0x91,0xef,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s16  d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x91,0xef,0x42,0x0f]
+# CHECK-V8: ^
+
+[0xa1,0xef,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s32  d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa1,0xef,0x42,0x0f]
+# CHECK-V8: ^
+
+[0x92,0xff,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s16  q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x92,0xff,0x42,0x0f]
+# CHECK-V8: ^
+
+[0xa2,0xff,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s32  q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa2,0xff,0x42,0x0f]
+# CHECK-V8: ^