[globalisel][tablegen] Add support for (set $dst, 1) and test X86's OptForSize predicate.

Summary:
It's rare but a small number of patterns use IntInit's at the root of the match.
On X86, one such rule is enabled by the OptForSize predicate and causes the
compiler to use the smaller:
	%0 = MOV32r1
instead of the usual:
	%0 = MOV32ri 1

This patch adds support for matching IntInit's at the root and uses this as a
test case for the optsize attribute that was implemented in r301750

Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D32791

llvm-svn: 303678

2 files changed, 122 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir
new file mode 100644
index 00000000000..93a7aba1d97
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir
@@ -0,0 +1,96 @@
+# RUN: llc -mtriple=i586-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK
+#
+# This is necessary to test that attribute-based rule predicates work and that
+# they properly reset between functions.
+
+--- |
+  define i32 @const_i32_1() {
+    ret i32 1
+  }
+
+  define i32 @const_i32_1_optsize() #0 {
+    ret i32 1
+  }
+
+  define i32 @const_i32_1b() {
+    ret i32 1
+  }
+
+  define i32 @const_i32_1_optsizeb() #0 {
+    ret i32 1
+  }
+
+  attributes #0 = { optsize }
+...
+---
+name:            const_i32_1
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK-LABEL: name: const_i32_1
+# CHECK:       registers:
+# CHECK-NEXT:  - { id: 0, class: gr32 }
+registers:
+  - { id: 0, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = MOV32ri 1
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s32) = G_CONSTANT i32 1
+    %eax = COPY %0(s32)
+    RET 0, implicit %eax
+...
+---
+name:            const_i32_1_optsize
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK-LABEL: name: const_i32_1_optsize
+# CHECK:       registers:
+# CHECK-NEXT:  - { id: 0, class: gr32 }
+registers:
+  - { id: 0, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = MOV32r1
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s32) = G_CONSTANT i32 1
+    %eax = COPY %0(s32)
+    RET 0, implicit %eax
+...
+---
+name:            const_i32_1b
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK-LABEL: name: const_i32_1b
+# CHECK:       registers:
+# CHECK-NEXT:  - { id: 0, class: gr32 }
+registers:
+  - { id: 0, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = MOV32ri 1
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s32) = G_CONSTANT i32 1
+    %eax = COPY %0(s32)
+    RET 0, implicit %eax
+...
+---
+name:            const_i32_1_optsizeb
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK-LABEL: name: const_i32_1_optsizeb
+# CHECK:       registers:
+# CHECK-NEXT:  - { id: 0, class: gr32 }
+registers:
+  - { id: 0, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = MOV32r1
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s32) = G_CONSTANT i32 1
+    %eax = COPY %0(s32)
+    RET 0, implicit %eax
+...
diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td
index aeac85962f6..8778ad71ea7 100644
--- a/llvm/test/TableGen/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter.td
@@ -462,6 +462,32 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1)
 def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
 def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
 
+//===- Test a simple pattern with just a leaf immediate. ------------------===//
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 2)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_CONSTANT) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* Operand 1 */ (MI0.getOperand(1).isCImm() && MI0.getOperand(1).getCImm()->equalsInt(1))))) {
+// CHECK-NEXT:      // 1:i32 => (MOV1:i32)
+// CHECK-NEXT:      MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MOV1));
+// CHECK-NEXT:      MIB.add(MI0.getOperand(0)/*dst*/);
+// CHECK-NEXT:      for (const auto *FromMI : {&MI0, })
+// CHECK-NEXT:        for (const auto &MMO : FromMI->memoperands())
+// CHECK-NEXT:          MIB.addMemOperand(MMO);
+// CHECK-NEXT:      I.eraseFromParent();
+// CHECK-NEXT:      MachineInstr &NewI = *MIB;
+// CHECK-NEXT:      constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:      return true;
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return false;
+// CHECK-NEXT:  }()) { return true; }
+
+def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>;
+
 //===- Test a pattern with an MBB operand. --------------------------------===//
 
 // CHECK-LABEL: if ([&]() {