diff options
| author | Jiangning Liu <jiangning.liu@arm.com> | 2014-07-24 01:29:59 +0000 |
|---|---|---|
| committer | Jiangning Liu <jiangning.liu@arm.com> | 2014-07-24 01:29:59 +0000 |
| commit | 451f30e89f882e796cbba744fc4f340b7ddbf43f (patch) | |
| tree | a539e0ce7cb525b8c17f76d144b7c955dc8638fc /llvm/test | |
| parent | 933cccf3fa81a928a026a88483d30d202c6b048e (diff) | |
| download | bcm5719-llvm-451f30e89f882e796cbba744fc4f340b7ddbf43f.tar.gz bcm5719-llvm-451f30e89f882e796cbba744fc4f340b7ddbf43f.zip | |
[AArch64] Disable some optimization cases for type conversion from sint to fp, because those optimization cases are micro-architecture dependent and only make sense for Cyclone. A new predicate Cyclone is introduced in .td file.
llvm-svn: 213827
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-scvt.ll | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-scvt.ll b/llvm/test/CodeGen/AArch64/arm64-scvt.ll index 2e006cff159..8baaf22238d 100644 --- a/llvm/test/CodeGen/AArch64/arm64-scvt.ll +++ b/llvm/test/CodeGen/AArch64/arm64-scvt.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s +; RUN: llc < %s -march=arm64 -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s +; RUN: llc < %s -march=arm64 -mcpu=cortex-a57 | FileCheck --check-prefix=CHECK-A57 %s ; rdar://13082402 define float @t1(i32* nocapture %src) nounwind ssp { @@ -409,6 +410,10 @@ define float @sfct1(i8* nocapture %sp0) { ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] +; CHECK-A57-LABEL: sfct1: +; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, #1] +; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]] +; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]] entry: %addr = getelementptr i8* %sp0, i64 1 %pix_sp0.0.copyload = load i8* %addr, align 1 @@ -466,6 +471,10 @@ define float @sfct5(i8* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] +; CHECK-A57-LABEL: sfct5: +; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, x1] +; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]] +; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]] entry: %addr = getelementptr i8* %sp0, i64 %offset %pix_sp0.0.copyload = load i8* %addr, align 1 @@ -536,6 +545,10 @@ define double @sfct10(i16* nocapture %sp0) { ; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] +; CHECK-A57-LABEL: sfct10: +; CHECK-A57: ldrsh w[[REGNUM:[0-9]+]], [x0, #2] +; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] +; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]] entry: %addr = getelementptr i16* %sp0, i64 1 %pix_sp0.0.copyload = load i16* %addr, align 1 @@ -592,6 +605,10 @@ define double @sfct14(i16* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] +; CHECK-A57-LABEL: sfct14: +; CHECK-A57: ldrsh w[[REGNUM:[0-9]+]], [x0, x1, lsl #1] +; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] +; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]] entry: %addr = getelementptr i16* %sp0, i64 %offset %pix_sp0.0.copyload = load i16* %addr, align 1 @@ -636,6 +653,10 @@ entry: ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] +; CHECK-A57-LABEL: sfct17: +; CHECK-A57: ldursb w[[REGNUM:[0-9]+]], [x0, #-1] +; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]] +; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]] %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* @@ -713,6 +734,10 @@ define double @sfct22(i16* nocapture %sp0) { ; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] +; CHECK-A57-LABEL: sfct22: +; CHECK-A57: ldursh w[[REGNUM:[0-9]+]], [x0, #1] +; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] +; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]] %bitcast = ptrtoint i16* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i16* |
