[AArch64] [ARM] Make a target-independent llvm.thread.pointer intrinsic.

Both AArch64 and ARM support llvm.<arch>.thread.pointer intrinsics that
just return the thread pointer.  I have a pending patch that does the same
for SystemZ (D19054), and there are many more targets that could benefit
from one.

This patch merges the ARM and AArch64 intrinsics into a single target
independent one that will also be used by subsequent targets.

Differential Revision: http://reviews.llvm.org/D19098

llvm-svn: 266818

5 files changed, 27 insertions, 8 deletions

diff --git a/llvm/test/Assembler/autoupgrade-thread-pointer.ll b/llvm/test/Assembler/autoupgrade-thread-pointer.ll
new file mode 100644
index 00000000000..a96829d9b2e
--- /dev/null
+++ b/llvm/test/Assembler/autoupgrade-thread-pointer.ll
@@ -0,0 +1,19 @@
+; Test autoupgrade of arch-specific thread pointer intrinsics
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+
+declare i8* @llvm.aarch64.thread.pointer()
+declare i8* @llvm.arm.thread.pointer()
+
+define i8* @test1() {
+; CHECK: test1()
+; CHECK: call i8* @llvm.thread.pointer()
+  %1 = call i8* @llvm.aarch64.thread.pointer()
+  ret i8 *%1
+}
+
+define i8* @test2() {
+; CHECK: test2()
+; CHECK: call i8* @llvm.thread.pointer()
+  %1 = call i8* @llvm.arm.thread.pointer()
+  ret i8 *%1
+}
diff --git a/llvm/test/CodeGen/AArch64/arm64-builtins-linux.ll b/llvm/test/CodeGen/AArch64/arm64-builtins-linux.ll
index 34fa1b47156..6caf3a2a18e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-builtins-linux.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-builtins-linux.ll
@@ -1,11 +1,11 @@
 ; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s
 
 ; Function Attrs: nounwind readnone
-declare i8* @llvm.aarch64.thread.pointer() #1
+declare i8* @llvm.thread.pointer() #1
 
 define i8* @thread_pointer() {
 ; CHECK: thread_pointer:
 ; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0
-  %1 = tail call i8* @llvm.aarch64.thread.pointer()
+  %1 = tail call i8* @llvm.thread.pointer()
   ret i8* %1
 }
diff --git a/llvm/test/CodeGen/ARM/thread_pointer.ll b/llvm/test/CodeGen/ARM/thread_pointer.ll
index c403fa5c4a2..fe1d3a4dfd0 100644
--- a/llvm/test/CodeGen/ARM/thread_pointer.ll
+++ b/llvm/test/CodeGen/ARM/thread_pointer.ll
@@ -3,8 +3,8 @@
 
 define i8* @test() {
 entry:
-	%tmp1 = call i8* @llvm.arm.thread.pointer( )		; <i8*> [#uses=0]
+	%tmp1 = call i8* @llvm.thread.pointer( )		; <i8*> [#uses=0]
 	ret i8* %tmp1
 }
 
-declare i8* @llvm.arm.thread.pointer()
+declare i8* @llvm.thread.pointer()
diff --git a/llvm/test/Transforms/SafeStack/AArch64/abi.ll b/llvm/test/Transforms/SafeStack/AArch64/abi.ll
index cdec923eb74..bd6710d160c 100644
--- a/llvm/test/Transforms/SafeStack/AArch64/abi.ll
+++ b/llvm/test/Transforms/SafeStack/AArch64/abi.ll
@@ -3,7 +3,7 @@
 
 define void @foo() nounwind uwtable safestack {
 entry:
-; CHECK: %[[TP:.*]] = call i8* @llvm.aarch64.thread.pointer()
+; CHECK: %[[TP:.*]] = call i8* @llvm.thread.pointer()
 ; CHECK: %[[SPA0:.*]] = getelementptr i8, i8* %[[TP]], i32 72
 ; CHECK: %[[SPA:.*]] = bitcast i8* %[[SPA0]] to i8**
 ; CHECK: %[[USP:.*]] = load i8*, i8** %[[SPA]]
diff --git a/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll b/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll
index da0f5e0a80a..5d584d0a76b 100644
--- a/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll
+++ b/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll
@@ -3,10 +3,10 @@
 
 define void @foo() nounwind uwtable safestack sspreq {
 entry:
-; The first @llvm.aarch64.thread.pointer is for the unsafe stack pointer, skip it.
-; TLS: call i8* @llvm.aarch64.thread.pointer()
+; The first @llvm.thread.pointer is for the unsafe stack pointer, skip it.
+; TLS: call i8* @llvm.thread.pointer()
 
-; TLS: %[[TP2:.*]] = call i8* @llvm.aarch64.thread.pointer()
+; TLS: %[[TP2:.*]] = call i8* @llvm.thread.pointer()
 ; TLS: %[[B:.*]] = getelementptr i8, i8* %[[TP2]], i32 40
 ; TLS: %[[C:.*]] = bitcast i8* %[[B]] to i8**
 ; TLS: %[[StackGuard:.*]] = load i8*, i8** %[[C]]